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Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1512-1517

2011

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Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography

IEEE transactions on very large scale integration (VLSI) systems, 2008-11, Vol.16 (11), p.1567-1580

2008

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Single- and Multi-core Configurable AES Architectures for Flexible Security

IEEE transactions on very large scale integration (VLSI) systems, 2010-04, Vol.18 (4), p.541-552

2010

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Built-in redundancy analysis for memory yield improvement

IEEE transactions on reliability, 2003-12, Vol.52 (4), p.386-399

2003

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A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography

IEEE transactions on circuits and systems. II, Express briefs, 2009-05, Vol.56 (5), p.394-398

2009

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Optimization of Pattern Matching Circuits for Regular Expression on FPGA

IEEE transactions on very large scale integration (VLSI) systems, 2007-12, Vol.15 (12), p.1303-1310

2007

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Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.120-125

2019

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AC-Plus Scan Methodology for Small Delay Testing and Characterization

IEEE transactions on very large scale integration (VLSI) systems, 2013-02, Vol.21 (2), p.329-341

2013

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MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy

2023 IEEE 41st International Conference on Computer Design (ICCD), 2023, p.614-622

2023

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Towards Efficient Visual Attention Prediction for 360 Degree Videos

2024 IEEE International Conference on Artificial Intelligence and eXtended and Virtual Reality (AIxVR), 2024, p.50-59

2024

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Reliability analysis and improvement for multi-level non-volatile memories with soft information

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.753-758

2011

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Efficient Dynamic Fixed-Point Quantization of CNN Inference Accelerators for Edge Devices

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2019, p.1-4

2019

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Fault simulation and test algorithm generation for random access memories

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-04, Vol.21 (4), p.480-490

2002

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AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010, p.340-348

2010

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A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.771-776

2011

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IoT: Source of test challenges

2016 21th IEEE European Test Symposium (ETS), 2016, p.1-10

2016

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Hardware-aware Model Architecture for Ternary Spiking Neural Networks

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), 2023, p.1-4

2023

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Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques

2008 17th Asian Test Symposium, 2008, p.245-250

2008

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HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration

2023 IEEE 36th International System-on-Chip Conference (SOCC), 2023, p.1-6

2023

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Efficient Hand Gesture Recognition using Multi-Task Multi-Modal Learning and Self-Distillation

Proceedings of the 5th ACM International Conference on Multimedia in Asia, 2023, p.1-7

2023

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Optimization of AI SoC with Compiler-assisted Virtual Design Platform

Proceedings of the 2023 International Symposium on Physical Design, 2023, p.187-193

2023

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High-performance architecture for Elliptic Curve Cryptography over binary field

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.3933-3936

2010

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Application-level embedded communication tracer for many-core systems

The 20th Asia and South Pacific Design Automation Conference, 2015, p.803-808

2015

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Automatic generation of memory built-in self-test cores for system-on-chip

Proceedings - Asian Test Symposium, 2001, p.91-96

2001

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Diagonal test and diagnostic schemes for flash memories

Proceedings - International Test Conference, 2002, p.37-46

2002

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Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications

Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography

Single- and Multi-core Configurable AES Architectures for Flexible Security

Built-in redundancy analysis for memory yield improvement

A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography

Optimization of Pattern Matching Circuits for Regular Expression on FPGA

Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators

AC-Plus Scan Methodology for Small Delay Testing and Characterization

MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy

Towards Efficient Visual Attention Prediction for 360 Degree Videos

Reliability analysis and improvement for multi-level non-volatile memories with soft information

Efficient Dynamic Fixed-Point Quantization of CNN Inference Accelerators for Edge Devices

Fault simulation and test algorithm generation for random access memories

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing

IoT: Source of test challenges

Hardware-aware Model Architecture for Ternary Spiking Neural Networks

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques

HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration

Efficient Hand Gesture Recognition using Multi-Task Multi-Modal Learning and Self-Distillation

Optimization of AI SoC with Compiler-assisted Virtual Design Platform

High-performance architecture for Elliptic Curve Cryptography over binary field

Application-level embedded communication tracer for many-core systems

Automatic generation of memory built-in self-test cores for system-on-chip

Diagonal test and diagnostic schemes for flash memories

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