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An efficient VLSI architecture for H.264 variable block size motion estimation

IEEE transactions on consumer electronics, 2005-11, Vol.51 (4), p.1291-1299

2005

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ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT

IEEE transactions on electron devices, 2016-08, Vol.63 (8), p.3036-3043

2016

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The auto-routing design tools for implementing touch sensor tracks

Microsystem technologies : sensors, actuators, systems integration, 2021-04, Vol.27 (4), p.1123-1131

2021

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The WSN and 3G/NFC embedded into IoV (Internet-of-Vehicle) fulfill cold chain logistics

Microsystem technologies : sensors, actuators, systems integration, 2018-10, Vol.24 (10), p.3977-3983

2018

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FPGA implementation of genetic vector quantizers

Neurocomputing (Amsterdam), 2010-06, Vol.73 (10), p.2125-2131

Ou, Chien-Min

2010

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Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Sensors (Basel, Switzerland), 2012-09, Vol.12 (9), p.11661-11683

2012

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High throughput and low area cost FPGA-based signature match circuit for network intrusion detection

Journal of the Chinese Institute of Engineers, 2009-04, Vol.32 (3), p.397-405

2009

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FPGA-based online learning hardware architecture for kernel fuzzy c-means algorithm

Indian journal of engineering and materials sciences, 2013-06, Vol.20 (3), p.225-231

2013

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Adaptive variable-rate motion vector quantization

Journal of the Chinese Institute of Engineers, 2006-04, Vol.29 (3), p.377-382

2006

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Low complexity adaptive error control for receiver-driven layered video multicast

Journal of the Chinese Institute of Engineers, 2006-11, Vol.29 (7), p.1215-1226

2006

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FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

VLSI Design, 2013-01, Vol.2013, p.1-10

2013

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Iterative optimization for joint design of source and channel codes using genetic algorithms

Journal of the Chinese Institute of Engineers, 2005-09, Vol.28 (5), p.803-810

2005

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VLSI architecture for motion vector quantization

IEEE transactions on consumer electronics, 2003-02, Vol.49 (1), p.237-242

2003

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Efficient Architecture For Island Genetic Algorithm in Reconfigurable Hardware

Intelligent automation and soft computing, 2012-01, Vol.18 (4), p.413-430

2012

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Design of Robust Communication Systems Using Genetic Algorithms

Genetic Programming, 2006, p.270-279

2006

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An Efficient Hardware-based Design for Network Intrusion Detection

WSEAS Transactions on Electronics, 2007-03, Vol.4 (3), p.49-55

Ou, Chien-Min

2007

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Robust vector qantization for burst error channels

Journal of the Chinese Institute of Engineers, 2004-07, Vol.27 (5), p.737-741

2004

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Efficient Logic Circuit for Network Intrusion Detection

Embedded and Ubiquitous Computing, 2006, p.776-784

2006

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Concurrent genetic optimization for joint design of source and channel codes

Neurocomputing (Amsterdam), 2006-12, Vol.70 (1), p.130-138

2006

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VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware

Algorithms and Architectures for Parallel Processing, p.513-524

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Genetic channel-optimized vector quantizer design for burst error channels

Neurocomputing (Amsterdam), 2005, Vol.63, p.345-357

2005

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Hybrid Genetic Algorithm for Design of Robust Communication Systems

Journal of software, 2006-09, Vol.1 (3)

2006

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A practice of 2-to-2 fixed priority arbiter used to multi-core processors

2017 International Conference on Applied System Innovation (ICASI), 2017, p.1217-1220

2017

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Efficient Header Classification Architecture for Network Intrusion Detection

Journal of Information Science and Engineering, 2009-11, Vol.25 (6), p.1839-1853

2009

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Service Discovery of IP Cameras Using SIP and Zeroconf Protocols

Autonomic and Trusted Computing, Vol.5060, p.388-402

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An efficient VLSI architecture for H.264 variable block size motion estimation

ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT

The auto-routing design tools for implementing touch sensor tracks

The WSN and 3G/NFC embedded into IoV (Internet-of-Vehicle) fulfill cold chain logistics

FPGA implementation of genetic vector quantizers

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

High throughput and low area cost FPGA-based signature match circuit for network intrusion detection

FPGA-based online learning hardware architecture for kernel fuzzy c-means algorithm

Adaptive variable-rate motion vector quantization

Low complexity adaptive error control for receiver-driven layered video multicast

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

Iterative optimization for joint design of source and channel codes using genetic algorithms

VLSI architecture for motion vector quantization

Efficient Architecture For Island Genetic Algorithm in Reconfigurable Hardware

Design of Robust Communication Systems Using Genetic Algorithms

An Efficient Hardware-based Design for Network Intrusion Detection

Robust vector qantization for burst error channels

Efficient Logic Circuit for Network Intrusion Detection

Concurrent genetic optimization for joint design of source and channel codes

VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware

Genetic channel-optimized vector quantizer design for burst error channels

Hybrid Genetic Algorithm for Design of Robust Communication Systems

A practice of 2-to-2 fixed priority arbiter used to multi-core processors

Efficient Header Classification Architecture for Network Intrusion Detection

Service Discovery of IP Cameras Using SIP and Zeroconf Protocols

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