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A 0.003 mm ^ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching

IEEE journal of solid-state circuits, 2015-06, Vol.50 (6), p.1382-1398

2015

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A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA

IEEE transactions on circuits and systems. I, Regular papers, 2015-04, Vol.62 (4), p.1005-1014

2015

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A 0.1-1.5GHz dual-mode Class-AB/Class-F power amplifier in 65nm CMOS

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013, p.372-375

2013

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A 0.1-1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, p.353-356

2014

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A 0.1-23-GHz SiGe BiCMOS analog multiplier and mixer based on attenuation-compensation technique

2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers, 2004, p.417-420

2004

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0,1,3维CeO_2的可控制备及CuO/CeO_2催化剂上CO氧化反应（英文）

催化学报, 2011, Vol.32 (8), p.1336-1341

单文娟刘畅郭红娟杨利华王晓楠冯兆池

2011

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0,1,3维CeO2的可控制备及CuO/CeO2催化剂上CO氧化反应

催化学报, 2011, Vol.32 (8), p.1336-1341

2011

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A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

Analog integrated circuits and signal processing, 2013-12, Vol.77 (3), p.567-582

2013

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A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, p.1-4

2012

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A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

Microelectronics, 2018-02, Vol.72, p.58-73

2018

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A 0.1-5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications

IEEE transactions on circuits and systems. I, Regular papers, 2014-11, Vol.61 (11), p.3266-3277

2014

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A 0.1–5.0 GHz SDR transmitter with current-mode power-mixer and self-calibration scheme in 65 nm CMOS

Microelectronics, 2017-12, Vol.70, p.1-11

2017

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A 0.1-5.0GHz self-calibrated SDR transmitter with −62.6dBc CIM3 in 65nm CMOS

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-4

2015

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A 0.1-5GHz flexible SDR receiver in 65nm CMOS

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, p.249-252

2014

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A 0.1-5GHz SDR transmitter with dual-mode power amplifier and digital-assisted I/Q imbalance calibration in 65nm CMOS

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, p.205-208

2013

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A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2015-05, Vol.23 (5), p.944-957

2015

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A 0.13µm CMOS 1.5-to-2.15GHz low power transmitter front-end for SDR applications

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.2453-2456

2011

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A 0.18-[Formula Omitted] CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

IEEE transactions on circuits and systems. I, Regular papers, 2009-11, Vol.56 (11), p.2498

2009

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A 0.18- \mu\hbox CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

IEEE transactions on circuits and systems. I, Regular papers, 2009-11, Vol.56 (11), p.2498-2510

2009

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A 0.18- muhbox m CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

IEEE transactions on circuits and systems. I, Regular papers, 2009-01, Vol.56 (11)

2009

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A 0.18-muhbox{m} CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

IEEE transactions on circuits and systems. I, Regular papers, 2009-11, Vol.56 (11), p.2498-2510

2009

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0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2014, p.179-181

2014

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A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.342-343

2013

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A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), 2014, p.195-198

2014

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A 0.003 mm ^ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching

A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA

A 0.1-1.5GHz dual-mode Class-AB/Class-F power amplifier in 65nm CMOS

A 0.1-1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration

A 0.1-23-GHz SiGe BiCMOS analog multiplier and mixer based on attenuation-compensation technique

0,1,3维CeO_2的可控制备及CuO/CeO_2催化剂上CO氧化反应（英文）

0,1,3维CeO2的可控制备及CuO/CeO2催化剂上CO氧化反应

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

A 0.1-5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications

A 0.1–5.0 GHz SDR transmitter with current-mode power-mixer and self-calibration scheme in 65 nm CMOS

A 0.1-5.0GHz self-calibrated SDR transmitter with −62.6dBc CIM3 in 65nm CMOS

A 0.1-5GHz flexible SDR receiver in 65nm CMOS

A 0.1-5GHz SDR transmitter with dual-mode power amplifier and digital-assisted I/Q imbalance calibration in 65nm CMOS

A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

A 0.13µm CMOS 1.5-to-2.15GHz low power transmitter front-end for SDR applications

A 0.18-[Formula Omitted] CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

A 0.18- \mu\hbox CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

A 0.18- muhbox m CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

A 0.18-muhbox{m} CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

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