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High-throughput one-dimensional median and weighted median filters on FPGA

IET computers & digital techniques, 2009-07, Vol.3 (4), p.384-394

2009

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Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array

IET computers & digital techniques, 2011-07, Vol.5 (4), p.271-286

2011

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Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

IET computers & digital techniques, 2009-05, Vol.3 (3), p.235-246

2009

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Average interconnection delay estimation for on-FPGA communication links

Electronics letters, 2007-08, Vol.43 (17), p.918-920

2007

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Synthesis of saturation arithmetic architectures

ACM transactions on design automation of electronic systems, 2003-07, Vol.8 (3), p.334-354

2003

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ROM to DSP block transfer for resource constrained synthesis

IET computers & digital techniques, 2007, Vol.1 (1), p.17-26

2007

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Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network

IEEE transactions on industrial electronics (1982), 2011-08, Vol.58 (8), p.3701-3716

2011

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Hardware architectures for eigenvalue computation of real symmetric matrices

IET computers & digital techniques, 2009, Vol.3 (1), p.72-84

2009

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A Steerable Complex Wavelet Construction and Its Implementation on FPGA

Field Programmable Logic and Application, 2004, p.394-403

2004

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Customizable elliptic curve cryptosystems

IEEE transactions on very large scale integration (VLSI) systems, 2005-09, Vol.13 (9), p.1048-1059

2005

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A Structured Methodology for System-on-an-FPGA Design

Field Programmable Logic and Application, 2004, p.1047-1051

2004

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Treatment of functional dyspepsia with sertraline：A double-blind randomized placebo-controlled pilot study

World journal of gastroenterology : WJG, 2012-11, Vol.18 (42), p.6127-6133

2012

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A Reconfigurable Platform for Real-Time Embedded Video Image Processing

Field Programmable Logic and Application, 2003, p.606-615

2003

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A Gaussian noise generator for hardware-based simulations

IEEE transactions on computers, 2004-12, Vol.53 (12), p.1523-1534

2004

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Run-time management of dynamically reconfigurable designs

Field-Programmable Logic and Applications From FPGAs to Computing Paradigm, 2006, p.59-68

2006

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Pipeline morphing and virtual pipelines

Field-Programmable Logic and Applications, 2005, p.111-120

2005

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Comparing three heuristic search methods for functional partitioning in hardware software codesign

Design automation for embedded systems, 2002-07, Vol.6 (4), p.425-449

2002

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Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization

Computer journal, 2011-01, Vol.54 (1), p.1-10

2011

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Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2006-05, Vol.53 (5), p.339-343

2006

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Optimum and heuristic synthesis of multiple word-length architectures

IEEE transactions on very large scale integration (VLSI) systems, 2005-01, Vol.13 (1), p.39-57

2005

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Comments on the BCS Lecture 'The Future of Computer Technology and its Implications for the Computer Industry' by Professor Steve Furber

Computer journal, 2008-11, Vol.51 (6), p.741-742

2008

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Average interconnection delay estimation for on-FPGA communication links

Electronics letters, 2007-08, Vol.43 (17), p.1-1

2007

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Video image processing with the Sonic architecture

Computer (Long Beach, Calif.), 2000-04, Vol.33 (4), p.50-57

2000

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Truncation noise in fixed-point SFGs

Electronics letters, 1999-11, Vol.35 (23), p.2012-2014

1999

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Prevention and management of hepatitis B virus reactivation in patients with hematological malignancies treated with anticancer therapy

World journal of gastroenterology : WJG, 2016-07, Vol.22 (28), p.6484-6500

2016

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High-throughput one-dimensional median and weighted median filters on FPGA

Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Average interconnection delay estimation for on-FPGA communication links

Synthesis of saturation arithmetic architectures

ROM to DSP block transfer for resource constrained synthesis

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network

Hardware architectures for eigenvalue computation of real symmetric matrices

A Steerable Complex Wavelet Construction and Its Implementation on FPGA

Customizable elliptic curve cryptosystems

A Structured Methodology for System-on-an-FPGA Design

Treatment of functional dyspepsia with sertraline：A double-blind randomized placebo-controlled pilot study

A Reconfigurable Platform for Real-Time Embedded Video Image Processing

A Gaussian noise generator for hardware-based simulations

Run-time management of dynamically reconfigurable designs

Pipeline morphing and virtual pipelines

Comparing three heuristic search methods for functional partitioning in hardware software codesign

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization

Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits

Optimum and heuristic synthesis of multiple word-length architectures

Comments on the BCS Lecture 'The Future of Computer Technology and its Implications for the Computer Industry' by Professor Steve Furber

Average interconnection delay estimation for on-FPGA communication links

Video image processing with the Sonic architecture

Truncation noise in fixed-point SFGs

Prevention and management of hepatitis B virus reactivation in patients with hematological malignancies treated with anticancer therapy

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