UB Paderborn / Katalog / Suche / in CDI

A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1943-1956

2022

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A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-11, Vol.40 (11), p.2386-2399

2021

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Scalable Construction of Clock Trees With Useful Skew and High Timing Quality

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-06, Vol.38 (6), p.1161-1174

2019

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Cost-Effective Robustness in Clock Networks Using Near-Tree Structures

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-04, Vol.34 (4), p.515-528

2015

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Fast and Optimal Redundant Via Insertion

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-12, Vol.27 (12), p.2197-2208

2008

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Routability-Driven Placement and White Space Allocation

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-05, Vol.26 (5), p.858-871

2007

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A Linear-Time Complex-Valued Eigenvalue Solver for Full-Wave Analysis of Large-Scale On-Chip Interconnect Structures

IEEE transactions on microwave theory and techniques, 2009-08, Vol.57 (8), p.2021-2029

2009

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Performance analysis of latency-insensitive systems

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-03, Vol.25 (3), p.469-483

2006

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An Automatic Design of Factors in a Human-Pose Estimation System Using Neural Networks

IEEE transactions on systems, man, and cybernetics. Systems, 2016-07, Vol.46 (7), p.875-887

2016

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Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-04, Vol.31 (4), p.532-545

2012

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Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-01, Vol.21 (1), p.81-92

2002

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Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

IEEE transactions on very large scale integration (VLSI) systems, 2010-11, Vol.18 (11), p.1621-1624

2010

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A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-03, Vol.31 (3), p.380-390

2012

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Optimization of placement solutions for routability

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-9

2013

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Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-10, Vol.25 (10), p.2062-2075

2006

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From O(k^N) to O(N) : A Fast and High-Capacity Eigenvalue Solver for Full-Wave Extraction of Very Large Scale On-Chip Interconnects

IEEE transactions on microwave theory and techniques, 2009-12, Vol.57 (12), p.3219-3228

2009

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From [Formula Omitted] to [Formula Omitted]: A Fast and High-Capacity Eigenvalue Solver for Full-Wave Extraction of Very Large Scale On-Chip Interconnects

IEEE transactions on microwave theory and techniques, 2009-12, Vol.57 (12), p.3219

2009

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Construction of reconfigurable clock trees for MCMM designs

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012, p.713-719

2012

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A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-04, Vol.29 (4), p.636-641

2010

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A 3-D-Point-Cloud System for Human-Pose Estimation

IEEE transactions on systems, man, and cybernetics. Systems, 2014-11, Vol.44 (11), p.1486-1497

2014

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Fast clock scheduling and an application to clock tree synthesis

Integration (Amsterdam), 2017-01, Vol.56, p.115-127

2017

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Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression

ACM transactions on design automation of electronic systems, 2016-09, Vol.21 (4), p.1-27

2016

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Distributed non-equilibrium Green's function algorithms for the simulation of nanoelectronic devices with scattering

Journal of applied physics, 2011-08, Vol.110 (4), p.043713-043713-14

2011

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Human-pose estimation with neural-network realization

2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2015, p.4059-4064

2015

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A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs

A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems

Scalable Construction of Clock Trees With Useful Skew and High Timing Quality

Cost-Effective Robustness in Clock Networks Using Near-Tree Structures

Fast and Optimal Redundant Via Insertion

Routability-Driven Placement and White Space Allocation

A Linear-Time Complex-Valued Eigenvalue Solver for Full-Wave Analysis of Large-Scale On-Chip Interconnect Structures

Performance analysis of latency-insensitive systems

An Automatic Design of Factors in a Human-Pose Estimation System Using Neural Networks

Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation

Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits

Optimization of placement solutions for routability

Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction

From O(k^N) to O(N) : A Fast and High-Capacity Eigenvalue Solver for Full-Wave Extraction of Very Large Scale On-Chip Interconnects

From [Formula Omitted] to [Formula Omitted]: A Fast and High-Capacity Eigenvalue Solver for Full-Wave Extraction of Very Large Scale On-Chip Interconnects

Construction of reconfigurable clock trees for MCMM designs

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing

A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks

A 3-D-Point-Cloud System for Human-Pose Estimation

Fast clock scheduling and an application to clock tree synthesis

Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression

Distributed non-equilibrium Green's function algorithms for the simulation of nanoelectronic devices with scattering

Human-pose estimation with neural-network realization

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