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NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3067-3080

2018

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Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design

IEEE transactions on electron devices, 2015-12, Vol.62 (12), p.4022-4028

2015

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Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array

IEEE electron device letters, 2016-07, Vol.37 (7), p.870-873

2016

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NbOx based oscillation neuron for neuromorphic computing

Applied physics letters, 2017-09, Vol.111 (10)

2017

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SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

Nature materials, 2018-04, Vol.17 (4), p.335-340

2018

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Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array

IEEE transactions on very large scale integration (VLSI) systems, 2016-12, Vol.24 (12), p.3460-3467

2016

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Physical Unclonable Function Exploiting Sneak Paths in Resistive Cross-point Array

IEEE transactions on electron devices, 2016-08, Vol.63 (8), p.3109-3115

2016

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Device and materials requirements for neuromorphic computing

Journal of physics. D, Applied physics, 2019-01, Vol.52 (11), p.113001

2019

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Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories

IEEE electron device letters, 2015-11, Vol.36 (11), p.1157-1159

2015

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A ferroelectric field effect transistor based synaptic weight cell

Journal of physics. D, Applied physics, 2018-10, Vol.51 (43), p.434001

2018

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Design of Ternary Neural Network With 3-D Vertical RRAM Array

IEEE transactions on electron devices, 2017-06, Vol.64 (6), p.2721-2727

2017

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MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-05, Vol.37 (5), p.1009-1022

2018

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X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design

IEEE transactions on circuits and systems. I, Regular papers, 2018-10, Vol.65 (10), p.3459-3468

2018

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Fully parallel write/read in resistive synaptic array for accelerating on-chip learning

Nanotechnology, 2015-11, Vol.26 (45), p.455204-455204

2015

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A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.496-498

2018

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Emerging Memory Technologies: Recent Trends and Prospects

IEEE solid state circuits magazine, 2016-01, Vol.8 (2), p.43-56

2016

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A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System

IEEE transactions on very large scale integration (VLSI) systems, 2017-05, Vol.25 (5), p.1611-1621

2017

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Understanding the resistive switching characteristics and mechanism in active SiOx-based resistive switching memory

Journal of applied physics, 2012-12, Vol.112 (12)

2012

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Electroforming and resistive switching in silicon dioxide resistive memory devices

RSC advances, 2015-01, Vol.5 (27), p.21215-21236

2015

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Is “Cholinergic” Stimulus Useful for Ulcerative Colitis Treatment?

Digestive diseases and sciences, 2020, Vol.65 (1), p.6-8

2020

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Study of polarity effect in SiOx-based resistive switching memory

Applied physics letters, 2012-07, Vol.101 (5)

2012

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Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration

IEEE journal on emerging and selected topics in circuits and systems, 2015-06, Vol.5 (2), p.194-204

2015

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Ferroelectric FET analog synapse for acceleration of deep neural network training

2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.6.2.1-6.2.4

2017

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Quasi-Analytical Model of 3-D Vertical-RRAM Array Architecture for MB-Level Design

IEEE transactions on electron devices, 2017-04, Vol.64 (4), p.1568-1574

2017

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Investigation of edge- and bulk-related resistive switching behaviors and backward-scan effects in SiOx-based resistive switching memory

Applied physics letters, 2013-11, Vol.103 (19)

2013

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NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design

Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array

NbOx based oscillation neuron for neuromorphic computing

SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array

Physical Unclonable Function Exploiting Sneak Paths in Resistive Cross-point Array

Device and materials requirements for neuromorphic computing

Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories

A ferroelectric field effect transistor based synaptic weight cell

Design of Ternary Neural Network With 3-D Vertical RRAM Array

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design

Fully parallel write/read in resistive synaptic array for accelerating on-chip learning

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

Emerging Memory Technologies: Recent Trends and Prospects

A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System

Understanding the resistive switching characteristics and mechanism in active SiOx-based resistive switching memory

Electroforming and resistive switching in silicon dioxide resistive memory devices

Is “Cholinergic” Stimulus Useful for Ulcerative Colitis Treatment?

Study of polarity effect in SiOx-based resistive switching memory

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration

Ferroelectric FET analog synapse for acceleration of deep neural network training

Quasi-Analytical Model of 3-D Vertical-RRAM Array Architecture for MB-Level Design

Investigation of edge- and bulk-related resistive switching behaviors and backward-scan effects in SiOx-based resistive switching memory

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