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Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor

Membranes (Basel), 2021-02, Vol.11 (2), p.103

2021

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A High-Current Kink Effect Free Z-Gate Poly-Si Thin-Film Transistor

IEEE electron device letters, 2016-07, Vol.37 (7), p.886-889

2016

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150-200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

Micromachines (Basel), 2020-05, Vol.11 (5), p.504

2020

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A Novel Self-Aligned Double-Channel Polysilicon Thin-Film Transistor

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.799-804

2013

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Dependence of Device Performances on Fin Ratios of AlGaN/GaN Nanoscale Fin-HEMTs

ECS journal of solid state science and technology, 2023-09, Vol.12 (9), p.95001

2023

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A Novel Self-Aligned Raised Source/Drain Polysilicon Thin-Film Transistor With a High-Current Structure

IEEE electron device letters, 2011-08, Vol.32 (8), p.1080-1082

2011

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Effect of Finger Pitch on the Driving Ability of a 40-nm MOSFET With Contact Etch Stop Layer Strain in Multifinger Gated Structure

IEEE transactions on electron devices, 2010-06, Vol.57 (6), p.1355-1361

2010

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Q-Factor Performance of 28 nm-Node High-K Gate Dielectric under DPN Treatment at Different Annealing Temperatures

Electronics (Basel), 2020-12, Vol.9 (12), p.2086

2020

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A novel thin-film transistor with step gate-overlapped lightly doped drain and raised source/drain design

Solid-state electronics, 2017-11, Vol.137, p.10-15

2017

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Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs

Electronics (Basel), 2020-12, Vol.9 (12), p.2095

2020

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GaN on Silicon Substrate With Various SiC Buffer Layer for UV Detecting Applications

IEEE sensors journal, 2010-08, Vol.10 (8), p.1291-1296

2010

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Resistance of Outmost Shell- and Embedded-End Contacts of Single- and Multi-Bridged Carbon Nanotubes

Journal of nanoscience and nanotechnology, 2014-03, Vol.14 (3), p.2663-2666

2014

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Thermal stress probing the channel-length modulation effect of nano n-type FinFETs

Microelectronics and reliability, 2018-04, Vol.83, p.260-270

2018

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Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

Modern physics letters. B, Condensed matter physics, statistical physics, applied physics, 2018-05, Vol.32 (15), p.1850157

2018

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A Novel High-Performance Poly-Silicon Thin-Film Transistor With a Double-Channel Structure

IEEE electron device letters, 2008-11, Vol.29 (11), p.1229-1231

2008

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Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

Semiconductors (Woodbury, N.Y.), 2017-12, Vol.51 (12), p.1650-1655

2017

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A novel InGaAs photodiode fabrication and its application

2013 IEEE 5th International Nanoelectronics Conference (INEC), 2013, p.495-497

2013

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Study of Drain Alloy for Antimony Substrate Vertical High Voltage Power Metal Oxide Semiconductor Field Effect Transistors

Japanese Journal of Applied Physics, 2008-04, Vol.47 (4R), p.2122

2008

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The effect of post-hydrogen annealing and multilayer channel structure on nano-crystalline silicon thin film transistor performance

Journal of physics. D, Applied physics, 2010-05, Vol.43 (19), p.195102-195102

2010

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High performance power VDMOSFETs with a split-gate floating np-well design

Semiconductor science and technology, 2008-12, Vol.23 (12), p.122001

2008

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Effect of Ge Composition on Infrared Detecting Performance of Strain Si/ -} Heterojunction on Preferentially Etched Silicon Substrate

IEEE sensors journal, 2010-08, Vol.10 (8), p.1337-1341

2010

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The impacts of control gate voltage on the cycling endurance of split gate flash memory

IEEE electron device letters, 2000-07, Vol.21 (7), p.359-361

2000

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CIP metrology improving the bump yield in photo-lithography process

2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2015, p.386-389

2015

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Reducing the rework in the photo-lithography process of wafer-bump assembly with quality management

2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2015, p.351-354

2015

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Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

IEEE electron device letters, 1999-08, Vol.20 (8), p.412-414

1999

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Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor

A High-Current Kink Effect Free Z-Gate Poly-Si Thin-Film Transistor

150-200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

A Novel Self-Aligned Double-Channel Polysilicon Thin-Film Transistor

Dependence of Device Performances on Fin Ratios of AlGaN/GaN Nanoscale Fin-HEMTs

A Novel Self-Aligned Raised Source/Drain Polysilicon Thin-Film Transistor With a High-Current Structure

Effect of Finger Pitch on the Driving Ability of a 40-nm MOSFET With Contact Etch Stop Layer Strain in Multifinger Gated Structure

Q-Factor Performance of 28 nm-Node High-K Gate Dielectric under DPN Treatment at Different Annealing Temperatures

A novel thin-film transistor with step gate-overlapped lightly doped drain and raised source/drain design

Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs

GaN on Silicon Substrate With Various SiC Buffer Layer for UV Detecting Applications

Resistance of Outmost Shell- and Embedded-End Contacts of Single- and Multi-Bridged Carbon Nanotubes

Thermal stress probing the channel-length modulation effect of nano n-type FinFETs

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

A Novel High-Performance Poly-Silicon Thin-Film Transistor With a Double-Channel Structure

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

A novel InGaAs photodiode fabrication and its application

Study of Drain Alloy for Antimony Substrate Vertical High Voltage Power Metal Oxide Semiconductor Field Effect Transistors

The effect of post-hydrogen annealing and multilayer channel structure on nano-crystalline silicon thin film transistor performance

High performance power VDMOSFETs with a split-gate floating np-well design

Effect of Ge Composition on Infrared Detecting Performance of Strain Si/ -} Heterojunction on Preferentially Etched Silicon Substrate

The impacts of control gate voltage on the cycling endurance of split gate flash memory

CIP metrology improving the bump yield in photo-lithography process

Reducing the rework in the photo-lithography process of wafer-bump assembly with quality management

Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

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