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Timing driven placement using physical net constraints

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.780-783

2001

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ATOMIC: A Low-Cost, Very-High-Speed, Local Communication Architecture

1993 International Conference on Parallel Processing - ICPP'93, 1993, Vol.1, p.39-46

1993

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Optimal routing algorithm and the diameter of the cube-connected cycles

IEEE transactions on parallel and distributed systems, 1993-10, Vol.4 (10), p.1172-1178

1993

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A queueing analysis of the performance of DQDB

IEEE/ACM transactions on networking, 1995-12, Vol.3 (6), p.872-881

1995

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Partitionable multistage interconnection networks. Part 2: Task migration schemes

Telecommunication systems, 2000-01, Vol.13 (1), p.45

2000

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Transistor chaining in static CMOS functional cells of arbitrary planar topology

Discrete Applied Mathematics, 1999-01, Vol.90 (1), p.89-114

1999

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Special Issue on Multimedia Processing and Technology

Journal of parallel and distributed computing, 1995-11, Vol.30 (2), p.107-110

1995

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Performance analysis of single-buffered multistage interconnection networks

IEEE transactions on communications, 1994-09, Vol.42 (9), p.2722-2729

1994

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A pin permutation algorithm for improving over-the-cell channel routing

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-08, Vol.14 (8), p.1030-1037

1995

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A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks

IEEE/ACM transactions on networking, 1995-12, Vol.3 (6), p.708-715

1995

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LILA: layout generation for iterative logic arrays

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-11, Vol.14 (11), p.1359-1369

1995

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Optimal algorithms for bubble sort based non-Manhattan channel routing

IEEE transactions on computer-aided design of integrated circuits and systems, 1994-05, Vol.13 (5), p.603-609

1994

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A database manager for cell based VLSI circuits

Computers in industry, 1996-09, Vol.30 (1), p.63-71

1996

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Architecture for distributed multimedia database systems

Computer communications, 1990, Vol.13 (4), p.217-231

1990

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Design of a multimedia object-oriented DBMS

Multimedia systems, 1995-11, Vol.3 (5-6), p.217-227

1995

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A preprocessor for improving channel routing hierarchical pin permutation

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-07, Vol.14 (7), p.896-903

1995

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Performance evaluation of circuit switched multistage interconnection networks using a hold strategy

IEEE transactions on parallel and distributed systems, 1992-09, Vol.3 (5), p.632-640

1992

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From logic to symbolic layout for gate matrix

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-02, Vol.11 (2), p.216-227

1992

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Optimal cell generation for dual independent layout styles

IEEE transactions on computer-aided design of integrated circuits and systems, 1991-06, Vol.10 (6), p.770-782

1991

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A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithms

IEEE transactions on computer-aided design of integrated circuits and systems, 1991-06, Vol.10 (6), p.685-697

1991

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Efficient Boolean matching algorithm for cell libraries

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994, p.36-39

1994

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Sequencer-based data path synthesis of regular iterative algorithms

31st Design Automation Conference, 1994, p.155-160

1994

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Detailed placement with net length constraints

The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings, 2003, p.22-27

2003

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Concurrent error detection in highly structured logic arrays

IEEE journal of solid-state circuits, 1987-08, Vol.22 (4), p.583-594

1987

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A pin permutation algorithm for improving over-the-cell channel routing

[1992] Proceedings 29th ACM/IEEE Design Automation Conference, 1992, p.594-599

1992

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Timing driven placement using physical net constraints

ATOMIC: A Low-Cost, Very-High-Speed, Local Communication Architecture

Optimal routing algorithm and the diameter of the cube-connected cycles

A queueing analysis of the performance of DQDB

Partitionable multistage interconnection networks. Part 2: Task migration schemes

Transistor chaining in static CMOS functional cells of arbitrary planar topology

Special Issue on Multimedia Processing and Technology

Performance analysis of single-buffered multistage interconnection networks

A pin permutation algorithm for improving over-the-cell channel routing

A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks

LILA: layout generation for iterative logic arrays

Optimal algorithms for bubble sort based non-Manhattan channel routing

A database manager for cell based VLSI circuits

Architecture for distributed multimedia database systems

Design of a multimedia object-oriented DBMS

A preprocessor for improving channel routing hierarchical pin permutation

Performance evaluation of circuit switched multistage interconnection networks using a hold strategy

From logic to symbolic layout for gate matrix

Optimal cell generation for dual independent layout styles

A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithms

Efficient Boolean matching algorithm for cell libraries

Sequencer-based data path synthesis of regular iterative algorithms

Detailed placement with net length constraints

Concurrent error detection in highly structured logic arrays

A pin permutation algorithm for improving over-the-cell channel routing

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