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Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

Electronics (Basel), 2023-09, Vol.12 (17), p.3574

2023

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Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

IEEE access, 2022, Vol.10, p.126074-126088

2022

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A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection

IEEE access, 2024-01, Vol.12, p.1-1

2024

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Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems

IEEE access, 2024, Vol.12, p.95720-95735

2024

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Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

Journal of low power electronics and applications, 2023-03, Vol.13 (1), p.2

2023

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Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme

IEEE transactions on computers, 2024-07, Vol.73 (7), p.1767-1779

2024

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Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores

IEEE MICRO, 2021-03, Vol.41 (2), p.64-71

2021

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Customizable Vector Acceleration in Extreme-Edge Computing: A RISC-V Software/Hardware Architecture Study on VGG-16 Implementation

Electronics (Basel), 2021-02, Vol.10 (4), p.518

2021

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A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021, p.1-4

2021

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IEEE_Xplore

Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2020, p.1-6

2020

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Exploring Variable Latency Dividers in Vector Hardware Accelerators

2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024, p.1-4

2024

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من الواقع إلى الخيال؟ أبو العنبس الصيمري وأبو الفتح الإسكندري: قراءة في مقامات بديع الزمان الهمذاني

Arabica, 2017-01, Vol.64 (1), p.28-49

2017

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Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022, p.237-240

2022

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Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores

2017 New Generation of CAS (NGCAS), 2017, p.45-48

2017

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Philip F. Kennedy (éd.), On Fiction and Adab in Medieval Arabic Literature: Wiesbaden, Harrassowitz Verlag (« Studies in Arabic Language and Literature », 6), 2005, xxii+326 p. ISBN 3-447-05182-5

Bulletin d'études orientales, 2009-09 (58), p.418-420

Cheikh-Moussa, Abdallah

2009

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Improving SET Fault Resilience by Exploiting Buffered DMR Microarchitecture

Proceedings of SIE 2022, p.233-238

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Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects

Applications in Electronics Pervading Industry, Environment and Society, p.15-21

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Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design

Applications in Electronics Pervading Industry, Environment and Society, p.42-48

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Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy

Proceedings of SIE 2023, p.363-368

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A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach

Applications in Electronics Pervading Industry, Environment and Society, p.36-41

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Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor

Applications in Electronics Pervading Industry, Environment and Society, p.300-306

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The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes

Applications in Electronics Pervading Industry, Environment and Society, 2018, Vol.512, p.89-97

2018

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Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor

Applications in Electronics Pervading Industry, Environment and Society, p.529-539

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A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer

Applications in Electronics Pervading Industry, Environment and Society, p.505-511

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Avarice ou sophistique, une lecture du "Livre des avares" d'al-Gahiz

Bulletin d'études orientales, 1999-01, Vol.51, p.209-227

MOUSSA, Abdallah CHEIKH

1999

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Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection

Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems

Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme

Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores

Customizable Vector Acceleration in Extreme-Edge Computing: A RISC-V Software/Hardware Architecture Study on VGG-16 Implementation

A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design

Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment

Exploring Variable Latency Dividers in Vector Hardware Accelerators

من الواقع إلى الخيال؟ أبو العنبس الصيمري وأبو الفتح الإسكندري: قراءة في مقامات بديع الزمان الهمذاني

Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration

Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores

Philip F. Kennedy (éd.), On Fiction and Adab in Medieval Arabic Literature: Wiesbaden, Harrassowitz Verlag (« Studies in Arabic Language and Literature », 6), 2005, xxii+326 p. ISBN 3-447-05182-5

Improving SET Fault Resilience by Exploiting Buffered DMR Microarchitecture

Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects

Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design

Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy

A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach

Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor

The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes

Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor

A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer

Avarice ou sophistique, une lecture du "Livre des avares" d'al-Gahiz

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