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Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

IEEE transactions on electron devices, 2012-04, Vol.59 (4), p.888-894

2012

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Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

IEEE transactions on electron devices, 2011-03, Vol.58 (3), p.677-683

2011

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Relative Study of Analog Performance, Linearity, and Harmonic Distortion Between Junctionless and Conventional SOI FinFETs at Elevated Temperatures

Journal of electronic materials, 2020-05, Vol.49 (5), p.3309-3316

2020

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Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field-Effect Transistor

IEEE transactions on electron devices, 2014-07, Vol.61 (7), p.2515-2522

2014

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On the implementation of a copyright protection scheme using digital image watermarking

Multimedia tools and applications, 2020-05, Vol.79 (19-20), p.13125-13138

2020

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T cell costimulation, checkpoint inhibitors and anti-tumor therapy

Journal of biosciences, 2020-12, Vol.45 (1), Article 50

2020

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Implementation of image copyright protection tool using hardware-software co-simulation

Multimedia tools and applications, 2021, Vol.80 (3), p.4263-4277

2021

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IFN-γ lowers tumor growth by increasing glycolysis and lactate production in a nitric oxide-dependent manner: implications for cancer immunotherapy

Frontiers in immunology, 2023-10, Vol.14, p.1282653-1282653

2023

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Hardware execution of a saliency map based digital image watermarking framework

Multimedia tools and applications, 2021-07, Vol.80 (18), p.27245-27258

2021

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Impact of a Spacer-Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

IEEE transactions on electron devices, 2013-03, Vol.60 (3), p.935-943

2013

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Intelligent Copyright Protection for Images

1, 2019

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Gate-on-germanium source tunnel field-effect transistor enabling sub-0.5-V operation

Japanese Journal of Applied Physics, 2014-10, Vol.53 (10), p.104201-1-104201-7

2014

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Asymmetric U-Shaped-Gated TFET for Low-Power Ana-Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.6430-6437

2022

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Optimization of Hetero-Gate-Dielectric Tunnel FET for Label-Free Detection and Identification of Biomolecules

IEEE transactions on electron devices, 2020-05, Vol.67 (5), p.2157-2164

2020

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Observation of Current Enhancement Due to Drain-Induced Drain Tunneling in Tunnel Field-Effect Transistors

Japanese Journal of Applied Physics, 2012-08, Vol.51 (8), p.084301-084301-4

2012

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Observation of Current Enhancement Due to Drain-Induced Drain Tunneling in Tunnel Field-Effect Transistors

Japanese Journal of Applied Physics, 2012-08, Vol.51 (8R), p.84301

2012

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A Comparison of Analog Performance, Linearity, and Distortion Characteristics Between Symmetric InGaAs and Asymmetric InGaAs/InP MOSFETs

IEEE transactions on electron devices, 2021-04, Vol.68 (4), p.1570-1576

2021

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A Judicious Exploitation of Electrical Characteristics of a Unique GeSn TFET With Corner-Point for Sensing S-Protein Biomarker

IEEE transactions on nanotechnology, 2024, Vol.23, p.467-473

2024

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Temperature Dependence of Analog Performance, Linearity, and Harmonic Distortion for a Ge-Source Tunnel FET

IEEE transactions on electron devices, 2020-03, Vol.67 (3), p.810-815

2020

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Study on linearity and harmonic distortion for a unique U-TFET in low-power analog/RF applications: The role of channel epilayer thickness

International journal of electronics and communications, 2023-08, Vol.168, p.154714, Article 154714

2023

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Role of Corner-Effect and Channel Epilayer Thickness on the Performance of a Unique pTFET-Based Biosensor (epiCOR-pTFET-Biosensor) Device in Sub-100-nm Gate Length

IEEE transactions on nanotechnology, 2021, Vol.20, p.678-686

2021

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Comparative analysis of performance and its stability against real-time non-ideal conditions between DG-TFET sensor and its MOS equivalent for a range of biomolecule detection: a design perspective

International journal of electronics and communications, 2024-04, Vol.177, p.155242, Article 155242

2024

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Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel

IEEE transactions on electron devices, 2011-12, Vol.58 (12), p.4250-4257

2011

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Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications

Technical review - IETE, 2022-03, Vol.39 (2), p.316-327

2022

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Architecture- and Gate-Oxide-Level Optimization of a Si-Based Asymmetric U-TFET for Low Power Operation: a Real-Time Gate/Drain Electrostatic Based Leakage Perspective

SILICON, 2022-11, Vol.14 (16), p.10719-10727

2022

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Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

Relative Study of Analog Performance, Linearity, and Harmonic Distortion Between Junctionless and Conventional SOI FinFETs at Elevated Temperatures

Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field-Effect Transistor

On the implementation of a copyright protection scheme using digital image watermarking

T cell costimulation, checkpoint inhibitors and anti-tumor therapy

Implementation of image copyright protection tool using hardware-software co-simulation

IFN-γ lowers tumor growth by increasing glycolysis and lactate production in a nitric oxide-dependent manner: implications for cancer immunotherapy

Hardware execution of a saliency map based digital image watermarking framework

Impact of a Spacer-Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

Intelligent Copyright Protection for Images

Gate-on-germanium source tunnel field-effect transistor enabling sub-0.5-V operation

Asymmetric U-Shaped-Gated TFET for Low-Power Ana-Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study

Optimization of Hetero-Gate-Dielectric Tunnel FET for Label-Free Detection and Identification of Biomolecules

Observation of Current Enhancement Due to Drain-Induced Drain Tunneling in Tunnel Field-Effect Transistors

Observation of Current Enhancement Due to Drain-Induced Drain Tunneling in Tunnel Field-Effect Transistors

A Comparison of Analog Performance, Linearity, and Distortion Characteristics Between Symmetric InGaAs and Asymmetric InGaAs/InP MOSFETs

A Judicious Exploitation of Electrical Characteristics of a Unique GeSn TFET With Corner-Point for Sensing S-Protein Biomarker

Temperature Dependence of Analog Performance, Linearity, and Harmonic Distortion for a Ge-Source Tunnel FET

Study on linearity and harmonic distortion for a unique U-TFET in low-power analog/RF applications: The role of channel epilayer thickness

Role of Corner-Effect and Channel Epilayer Thickness on the Performance of a Unique pTFET-Based Biosensor (epiCOR-pTFET-Biosensor) Device in Sub-100-nm Gate Length

Comparative analysis of performance and its stability against real-time non-ideal conditions between DG-TFET sensor and its MOS equivalent for a range of biomolecule detection: a design perspective

Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel

Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications

Architecture- and Gate-Oxide-Level Optimization of a Si-Based Asymmetric U-TFET for Low Power Operation: a Real-Time Gate/Drain Electrostatic Based Leakage Perspective

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