UB Paderborn / Katalog / Suche / in CDI

QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-11, Vol.28 (11), p.1756-1766

2009

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IEEE_Xplore

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

IEEE transactions on very large scale integration (VLSI) systems, 2014-03, Vol.22 (3), p.621-630

2014

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IEEE_Xplore

Cell-Based Process Resilient Multiphase Clock Generation

IEEE transactions on very large scale integration (VLSI) systems, 2013-12, Vol.21 (12), p.2348-2352

2013

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IEEE_Xplore

Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-05, Vol.28 (5), p.764-769

2009

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IEEE_Xplore

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism

IEEE transactions on circuits and systems. I, Regular papers, 2013-04, Vol.60 (4), p.908-917

2013

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IEEE_Xplore

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

IEEE transactions on very large scale integration (VLSI) systems, 2013-12, Vol.21 (12), p.2240-2249

2013

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IEEE_Xplore

Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-05, Vol.29 (5), p.834-839

2010

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IEEE_Xplore

AC-Plus Scan Methodology for Small Delay Testing and Characterization

IEEE transactions on very large scale integration (VLSI) systems, 2013-02, Vol.21 (2), p.329-341

2013

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IEEE_Xplore

Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2007-08, Vol.54 (8), p.690-694, Article 690

2007

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IEEE_Xplore

A fully cell-based design for timing measurement of memory

2011 IEEE International Test Conference, 2011, p.1-10

2011

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IEEE_Xplore

Output test compression for compound defect diagnosis

2009 IEEE 8th International Conference on ASIC, 2009, p.569-572

2009

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IEEE_Xplore

Two-Gear Low-Power Scan Test

2008 17th Asian Test Symposium, 2008, p.337-342

2008

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IEEE_Xplore

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010, p.340-348

2010

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IEEE_Xplore

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting

IEEE design & test of computers, 2008-03, Vol.25 (2), p.132-140

2008

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IEEE_Xplore

QC-fill: an X-fill method for quick-and-cool scan test

Proceedings of the Conference on Design, Automation and Test in Europe, 2009, p.1142-1147

2009

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Verfügbarkeit prüfen

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

ACM transactions on design automation of electronic systems, 2008-01, Vol.13 (1), p.1-27

2008

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Verfügbarkeit prüfen

Case study of yield learning through in-house flow of volume diagnosis

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 2013, p.1-4

2013

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IEEE_Xplore

Low-jitter code-jumping for all-digital PLL to support almost continuous frequency tracking

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, 2011, p.1-4

2011

Link zum Volltext
IEEE_Xplore

Cell-Based Process Resilient Multiphase Clock Generation

IEEE transactions on very large scale integration (VLSI) systems, 2013, Vol.21 (12), p.2349-2352

2013

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Verfügbarkeit prüfen

Case study of process and design performance debugging with Digital Speed Sensor

VLSI Design, Automation and Test(VLSI-DAT), 2015, p.1-4

2015

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Verfügbarkeit prüfen

iScan: Indirect-access scan test over HOY test platform

2009 International Symposium on VLSI Design, Automation and Test, 2009, p.60-63

2009

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IEEE_Xplore

A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains

2006 International Symposium on VLSI Design, Automation and Test, 2006, p.1-4

2006

Link zum Volltext
IEEE_Xplore

Use of Multicasting-Scan Architectures for Compound Defect Diagnosis

2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, 2009, p.1-4

2009

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IEEE_Xplore

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012, p.1-4

2012

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IEEE_Xplore

QC-Fill: An X-Fill method for quick-and-cool scan test

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.1142-1147

2009

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IEEE_Xplore

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Weitere Dienste

Einstellungen

QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

Cell-Based Process Resilient Multiphase Clock Generation

Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression

AC-Plus Scan Methodology for Small Delay Testing and Characterization

Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain

A fully cell-based design for timing measurement of memory

Output test compression for compound defect diagnosis

Two-Gear Low-Power Scan Test

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting

QC-fill: an X-fill method for quick-and-cool scan test

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

Case study of yield learning through in-house flow of volume diagnosis

Low-jitter code-jumping for all-digital PLL to support almost continuous frequency tracking

Cell-Based Process Resilient Multiphase Clock Generation

Case study of process and design performance debugging with Digital Speed Sensor

iScan: Indirect-access scan test over HOY test platform

A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains

Use of Multicasting-Scan Architectures for Compound Defect Diagnosis

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property

QC-Fill: An X-Fill method for quick-and-cool scan test

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