UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

DRC Violation Prediction After Global Route Through Convolutional Neural Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-09, Vol.31 (9), p.1425-1438

2023

Volltextzugriff (PDF)

CNN-Based Stochastic Regression for IDDQ Outlier Identification

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

Volltextzugriff (PDF)

Methodology of Generating Timing-Slack-Based Cell-Aware Tests

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.5057-5070

2022

Volltextzugriff (PDF)

Outlier Detection for Analog Tests Using Deep Learning Techniques

2023 IEEE 41st VLSI Test Symposium (VTS), 2023, p.1-7

2023

Volltextzugriff (PDF)

Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information

2023 IEEE International Test Conference (ITC), 2023, p.357-366

2023

Volltextzugriff (PDF)

Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods

2024 IEEE 42nd VLSI Test Symposium (VTS), 2024, p.1-7

2024

Volltextzugriff (PDF)

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks

2021 IEEE 39th VLSI Test Symposium (VTS), 2021, p.1-7

2021

Volltextzugriff (PDF)

CNN-based Stochastic Regression for IDDQ Outlier Identification

2020 IEEE 38th VLSI Test Symposium (VTS), 2020, p.1-6

2020

Volltextzugriff (PDF)

Methodology of Generating Timing-Slack-Based Cell-Aware Tests

2019 IEEE International Test Conference (ITC), 2019, p.1-10

2019

Volltextzugriff (PDF)

Fast WAT test structure for measuring Vt variance based on latch-based comparators

2017 IEEE 35th VLSI Test Symposium (VTS), 2017, p.1-6

2017

Volltextzugriff (PDF)

A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-02, Vol.29 (2), p.240-245

2010

Volltextzugriff (PDF)

DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023, p.313-319

2023

Volltextzugriff (PDF)

Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2019, p.1-4

2019

Volltextzugriff (PDF)

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks

IEEE transactions on semiconductor manufacturing, 2024-08, Vol.37 (3), p.280-292

2024

Volltextzugriff (PDF)

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

Integration (Amsterdam), 2004-12, Vol.38 (2), p.245-265

2004

Volltextzugriff (PDF)

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051), 1999, p.364-368

1999

Volltextzugriff (PDF)

Cost reduction and test-quality control for scan-based testing of statistical timing defect

Chao, Mango Chia-Tso

2006

Volltextzugriff (PDF)

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, 1999, p.364-369

1999

Volltextzugriff (PDF)

1 – 18 von 18

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(6)
Mit Volltextzugriff
(17)

Publikationsform

Sprache

Englisch
(18)

Erscheinungsjahr

n.n

Thema

Engineering
(14)
Engineering, Electrical & Electronic
(14)
Science & Technology
(14)
Technology
(14)
Computer Science
(13)
Computer Science, Hardware & Architecture
(10)
Artificial Neural Networks
(6)
Integrated Circuits
(5)
Computer Science, Theory & Methods
(4)
Predictive Models
(4)
Very Large Scale Integration
(4)
Computer Science, Interdisciplinary Applications
(3)
Correlation
(3)
Data Analysis
(3)
Delay
(3)
Methodology
(3)
Neural Networks
(3)
Outliers
(3)
Regression Models
(3)
Training
(3)

15 weitere anzeigen...

Weniger anzeigen...

Kollektion

IEEE/IET Electronic Library
(15)
IngentaConnect
(6)
ACM Digital Library
(3)
ProQuest Dissertations & Theses A&I
(1)
Elsevier ScienceDirect Journals Complete
(1)

Zeitschrift / Serie

Menü

Weitere Dienste

Einstellungen

DRC Violation Prediction After Global Route Through Convolutional Neural Network

CNN-Based Stochastic Regression for IDDQ Outlier Identification

Methodology of Generating Timing-Slack-Based Cell-Aware Tests

Outlier Detection for Analog Tests Using Deep Learning Techniques

Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information

Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks

CNN-based Stochastic Regression for IDDQ Outlier Identification

Methodology of Generating Timing-Slack-Based Cell-Aware Tests

Fast WAT test structure for measuring Vt variance based on latch-based comparators

A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations

DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network

Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

Cost reduction and test-quality control for scan-based testing of statistical timing defect

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

Suchergebnisse filtern