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Impacts of gate structure on dynamic threshold SOI nMOSFETs

IEEE electron device letters, 2002-08, Vol.23 (8), p.497-499

2002

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Systematical Study of Reliability Issues in Plasma-Nitrided and Thermally Nitrided Oxides for Advanced Dual-Gate Oxide p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Japanese Journal of Applied Physics, 2007-03, Vol.46 (3R), p.1124

2007

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high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

IEEE transactions on electron devices, 2000-12, Vol.47 (12), p.2379-2384

2000

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Reduced reverse narrow channel effect in thin SOI nMOSFETs

IEEE electron device letters, 2000-09, Vol.21 (9), p.460-462

2000

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An anomalous crossover in Vth roll-off for indium-doped nMOSFETs

IEEE electron device letters, 2000-09, Vol.21 (9), p.457-459

2000

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The Effects of Super-Steep-Retrograde Indium Channel Profile on Deep Submicron n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Japanese Journal of Applied Physics, 2001-01, Vol.40 (1R), p.75-79

2001

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A novel sacrificial gate stack process for suppression of boron penetration in p-MOSFET with shallow BF2-implanted source/drain extension

IEEE electron device letters, 2000-08, Vol.21 (8), p.381

2000

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A Low Thermal Budget High Performance 0.25–0.18 µm Merged Logic Device and Dynamic Random Access Memory Application

Japanese Journal of Applied Physics, 2000-04, Vol.39 (4S), p.2162

2000

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High performance 0.1 /spl mu/m dynamic threshold MOSFET using indium channel implantation

IEEE electron device letters, 2000-03, Vol.21 (3), p.127-129

2000

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High performance 0.1 mu m dynamic threshold MOSFET using indiumchannel implantation

IEEE electron device letters, 2000-03, Vol.21 (3), p.127-129

2000

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High performance 0.1 [micro]m dynamic threshold MOSFET using indium channel implantation

IEEE electron device letters, 2000-03, Vol.21 (3), p.127

2000

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A novel sacrificial gate stack process for suppression of boron penetration in p-MOSFET with shallow BF/sub 2/-implanted source/drain extension

IEEE electron device letters, 2000-08, Vol.21 (8), p.381-383

2000

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A novel sacrificial gate stack process for suppression of boron penetration in p-MOSFET with shallow BF sub(2)-implanted source/drain extension

IEEE electron device letters, 2000-08, Vol.21 (8), p.381-383

2000

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A novel sacrificial gate stack process for suppression of boronpenetration in p-MOSFET with shallow BF(2)-implantedsource/drain extension

IEEE electron device letters, 2000-08, Vol.21 (8), p.381-383

2000

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The Combined Effects of Nitrogen Implantation at S/D Extension and N 2 O Oxide on 0.18 µm N- and P-Metal Oxide Field Effect Transistors (MOSFETs)

Japanese Journal of Applied Physics, 1999-12, Vol.38 (12A), p.L1366

1999

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Low thermal budget high performance 0.25-0.18 mu m merged logic device and dynamic random access memory application

JPN J APPL PHYS PART 1 REGUL PAP SHORT NOTE REV PAP, 2000-01, Vol.39 (5 B), p.2162-2166

2000

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Impacts of gate structure on dynamic threshold SOI nMOSFETs

Systematical Study of Reliability Issues in Plasma-Nitrided and Thermally Nitrided Oxides for Advanced Dual-Gate Oxide p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

Reduced reverse narrow channel effect in thin SOI nMOSFETs

An anomalous crossover in Vth roll-off for indium-doped nMOSFETs

The Effects of Super-Steep-Retrograde Indium Channel Profile on Deep Submicron n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

A novel sacrificial gate stack process for suppression of boron penetration in p-MOSFET with shallow BF2-implanted source/drain extension

A Low Thermal Budget High Performance 0.25–0.18 µm Merged Logic Device and Dynamic Random Access Memory Application

High performance 0.1 /spl mu/m dynamic threshold MOSFET using indium channel implantation

High performance 0.1 mu m dynamic threshold MOSFET using indiumchannel implantation

High performance 0.1 [micro]m dynamic threshold MOSFET using indium channel implantation

A novel sacrificial gate stack process for suppression of boron penetration in p-MOSFET with shallow BF/sub 2/-implanted source/drain extension

A novel sacrificial gate stack process for suppression of boron penetration in p-MOSFET with shallow BF sub(2)-implanted source/drain extension

A novel sacrificial gate stack process for suppression of boronpenetration in p-MOSFET with shallow BF(2)-implantedsource/drain extension

The Combined Effects of Nitrogen Implantation at S/D Extension and N 2 O Oxide on 0.18 µm N- and P-Metal Oxide Field Effect Transistors (MOSFETs)

Low thermal budget high performance 0.25-0.18 mu m merged logic device and dynamic random access memory application

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