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An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box-Muller Method

IEEE access, 2023, Vol.11, p.64745-64757

2023

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Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization

IET circuits, devices & systems, 2021-08, Vol.15 (5), p.475-484

2021

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Efficient Realization of BCD Multipliers Using FPGAs

International Journal of Reconfigurable Computing, 2017-01, Vol.2017 (2017), p.1-12-002

2017

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Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures

Computers & electrical engineering, 2022-09, Vol.102, p.108294, Article 108294

2022

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Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture

Journal of circuits, systems, and computers, 2020-09, Vol.29 (12), p.2050200

2020

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Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

International Journal of Reconfigurable Computing, 2009-01, Vol.2009 (2009), p.5-15

2009

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Optimized FPGA-Based 16-bits Squarers Using LUTs and a Divide-and-Conquer Approach

2024 International Conference on Computing, Internet of Things and Microwave Systems (ICCIMS), 2024, p.1-4

2024

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FPGA-Based 8x8 Bits Signed Multipliers Using LUTs

2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), 2023, p.366-370

2023

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VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing

Journal of circuits, systems, and computers, 2017-09, Vol.26 (9), p.1750129

2017

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FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input

2023 IEEE 13th Annual Computing and Communication Workshop and Conference (CCWC), 2023, p.0218-0221

2023

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Optimized FPGA-Based Datapath for the Iterative Design for the Factorial Function

2022 IEEE 13th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), 2022, p.0532-0534

2022

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FPGA-Based Designs of the Factorial Function

2022 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), 2022, p.16-20

2022

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FPGA realization of high performance large size computational functions: multipliers and applications

Analog integrated circuits and signal processing, 2012-02, Vol.70 (2), p.165-179

2012

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Symmetric Large Size Unsigned Multiplication Using Embedded DSP Blocks in FPGAs

2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), 2021, p.0749-0753

2021

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Frequency Optimized FPGA-Based Digital FIR Filters with Data Inputs and Coefficients of Large Size

2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), 2021, p.0760-0764

2021

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Level-converter aware supply voltage scaling for reducing dynamic power dissipation in clocked sequential designs

2009 International Conference on Multimedia Computing and Systems, 2009, p.102-105

Chabini, N.

2009

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Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter

2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), 2023, p.377-380

2023

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A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, p.64-74

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An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs

2022 IEEE 3rd International Conference on Electronics, Control, Optimization and Computer Science (ICECOCS), 2022, p.1-3

2022

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Efficient Realization of Large Size Two’s Complement Multipliers Using Embedded Blocks in FPGAs

Circuits, systems, and signal processing, 2008-10, Vol.27 (5), p.713-731

2008

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Design optimization of the quantization and a pipelined 2D-DCT for real-time applications

Multimedia tools and applications, 2013-12, Vol.67 (3), p.667-685

2013

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Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

IEEE transactions on very large scale integration (VLSI) systems, 2004-06, Vol.12 (6), p.573-589

2004

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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

IEEE transactions on very large scale integration (VLSI) systems, 2005-10, Vol.13 (10), p.1113-1126

2005

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Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks

2023 IEEE World AI IoT Congress (AIIoT), 2023, p.0730-0735

2023

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An approach for efficient realization of multi-operand addition on FPGAs using ternary-adders

2017 8th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), 2017, p.46-48

2017

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An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box-Muller Method

Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization

Efficient Realization of BCD Multipliers Using FPGAs

Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures

Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture

Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

Optimized FPGA-Based 16-bits Squarers Using LUTs and a Divide-and-Conquer Approach

FPGA-Based 8x8 Bits Signed Multipliers Using LUTs

VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing

FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input

Optimized FPGA-Based Datapath for the Iterative Design for the Factorial Function

FPGA-Based Designs of the Factorial Function

FPGA realization of high performance large size computational functions: multipliers and applications

Symmetric Large Size Unsigned Multiplication Using Embedded DSP Blocks in FPGAs

Frequency Optimized FPGA-Based Digital FIR Filters with Data Inputs and Coefficients of Large Size

Level-converter aware supply voltage scaling for reducing dynamic power dissipation in clocked sequential designs

Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter

A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs

An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs

Efficient Realization of Large Size Two’s Complement Multipliers Using Embedded Blocks in FPGAs

Design optimization of the quantization and a pipelined 2D-DCT for real-time applications

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks

An approach for efficient realization of multi-operand addition on FPGAs using ternary-adders

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