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VCSEL-based optical links in burst-mode slow optical power ramp-up and how to achieve ultra-short wake-up times

Electronics letters, 2017-09, Vol.53 (19), p.1325-1327

2017

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Feedback delay reduction of Tomlinson–Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic

Electronics letters, 2016-11, Vol.52 (23), p.1906-1908

2016

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Design Automation for Differential MOS Current-Mode Logic Circuits

1st ed. 2019., 2018

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Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

IEEE journal on emerging and selected topics in circuits and systems, 2012-06, Vol.2 (2), p.295-306

2012

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Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.1772-1775

2011

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Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.1014-1019

2011

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A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C228-C229

2015

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A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS

2018 IEEE Symposium on VLSI Circuits, 2018, p.53-54

2018

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A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET

2017 Symposium on VLSI Circuits, 2017, p.C320-C321

2017

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4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS

2018 Optical Fiber Communications Conference and Exposition (OFC), 2018, p.1-3

2018

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Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2010, p.149-154

2010

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FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, 2009, p.267-270

2009

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A 5.35 mm2 10GBASE-T Ethernet LDPC decoder chip in 90 nm CMOS

2010 IEEE Asian Solid-State Circuits Conference, 2010, p.1-4

2010

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Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

2009 IEEE Workshop on Signal Processing Systems, 2009, p.115-120

2009

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A flexible DSP block to enhance FPGA arithmetic performance

2009 International Conference on Field-Programmable Technology, 2009, p.70-77

2009

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Using 3D integration technology to realize multi-context FPGAs

2009 International Conference on Field Programmable Logic and Applications, 2009, p.507-510

2009

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A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

IEEE journal of solid-state circuits, 2018-12, Vol.53 (12), p.3508-3516

2018

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A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.38-48

2020

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A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

IEEE journal of solid-state circuits, 2018-11, Vol.53 (11), p.3268-3279

2018

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An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

IEEE journal of solid-state circuits, 2018-03, Vol.53 (3), p.861-872

2018

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A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

IEEE journal of solid-state circuits, 2017-12, Vol.52 (12), p.3458-3473

2017

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A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.1214-1226

2018

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A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.104-106

2018

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A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.1227-1237

2018

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A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.358-360

2018

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VCSEL-based optical links in burst-mode slow optical power ramp-up and how to achieve ultra-short wake-up times

Feedback delay reduction of Tomlinson–Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic

Design Automation for Differential MOS Current-Mode Logic Circuits

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS

A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET

4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation

A 5.35 mm2 10GBASE-T Ethernet LDPC decoder chip in 90 nm CMOS

Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

A flexible DSP block to enhance FPGA arithmetic performance

Using 3D integration technology to realize multi-context FPGAs

A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET

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