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CMOS fully integrated reconfigurable power amplifier with efficiency enhancement for LTE applications

Electronics letters, 2015-01, Vol.51 (2), p.181-183

2015

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Robustness Assessment Through 77GHz Operating Life Test of Power Amplifier for Radar Applications in 28nm FD-SOI CMOS

2024 IEEE International Reliability Physics Symposium (IRPS), 2024, p.4B.3-1-4B.3-6

2024

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Advanced 200-mm RF SOI Technology exhibiting 78\ \text\ \mathrm}\times \mathrm} and 3.7 V breakdown voltage targeting sub 6 GHz 5G FEM

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2022, p.191-194

2022

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A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2008-04, Vol.55 (4), p.344-348

2008

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A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.330-331

2013

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Aging control of power amplifier using power detector

2018 International Integrated Reliability Workshop (IIRW), 2018, p.1-4

2018

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A fully integrated CMOS PM radio receiver for wristwatch calibration

IEEE journal of solid-state circuits, 1998-07, Vol.33 (7), p.1014-1022

1998

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Reconfigurable wide-band receiver with positive feed-back translational loop

2011 IEEE Radio Frequency Integrated Circuits Symposium, 2011, p.1-4

2011

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A 27.5-dBm linear reconfigurable CMOS power amplifier for 3GPP LTE applications

2011 IEEE 9th International New Circuits and systems conference, 2011, p.221-224

2011

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Wide-band receiver architecture with flexible blocker filtering techniques

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010, p.894-897

2010

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A cost effective RF-SOI Drain Extended MOS transistor featuring PSAT=19dBm @28GHz & VDD=3V for 5G Power Amplifier application

2023 International Electron Devices Meeting (IEDM), 2023, p.1-4

2023

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2.2 V 300 mu A RDS pager baseband decoder

Digest of technical papers - IEEE International Solid-State Circuits Conference, 1997, Vol.40, p.300-301

1997

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The first experimental demonstration of a SASP-based full Software Radio receiver

2009 IEEE Radio Frequency Integrated Circuits Symposium, 2009, p.25-28

2009

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A 12.7dBm IIP3, 1.34dB NF, 4.9GHz–5.9GHz 802.11a/n LNA in 0.13 µm PD-SOI CMOS with Body-Contacted transistor

2016 IEEE MTT-S International Microwave Symposium (IMS), 2016, p.1-3

2016

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Activity profiling: Review of different solutions to develop reliable and performant design

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2016, p.47-50

2016

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A highly linear and tunable feed forward current source active inductor in 65nm CMOS technology for mobile applications

WAMICON 2011 Conference Proceedings, 2011, p.1-6

2011

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From Software-Defined to Software Radio: Analog Signal Processor features

2009 IEEE Radio and Wireless Symposium, 2009, p.348-351

2009

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65nm CMOS Circuit design of a sampled analog signal processor dedicated to RF applications

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008, p.233-236

2008

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A 2.2 V 300 /spl mu/A RDS pager baseband decoder

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997, p.300-301

1997

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A fully-integrated CMOS AM radio receiver for wrist-watch calibration

Proceedings of the 23rd European Solid-State Circuits Conference, 1997, p.84-87

1997

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Fragmentation in spin ice from magnetic charge injection

Nature communications, 2017-08, Vol.8 (1), p.209-6, Article 209

2017

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Nanoscale CMOS Transceiver Design in the 90-170-GHz Range

IEEE transactions on microwave theory and techniques, 2009-12, Vol.57 (12), p.3477-3490

2009

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A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3% DC-to-RF Efficiency, and 1-GHz Divided-Down Output

IEEE journal of solid-state circuits, 2016-09, Vol.51 (9), p.2054-2065

2016

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Impact of Aging Degradation on Heavy-Ion SEU Response of 28-nm UTBB FD-SOI Technology

IEEE transactions on nuclear science, 2022-08, Vol.69 (8), p.1865-1875

2022

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Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR

Solid-state electronics, 2022-05, Vol.191, p.108297, Article 108297

2022

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CMOS fully integrated reconfigurable power amplifier with efficiency enhancement for LTE applications

Robustness Assessment Through 77GHz Operating Life Test of Power Amplifier for Radar Applications in 28nm FD-SOI CMOS

Advanced 200-mm RF SOI Technology exhibiting 78\ \text\ \mathrm}\times \mathrm} and 3.7 V breakdown voltage targeting sub 6 GHz 5G FEM

A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS

Aging control of power amplifier using power detector

A fully integrated CMOS PM radio receiver for wristwatch calibration

Reconfigurable wide-band receiver with positive feed-back translational loop

A 27.5-dBm linear reconfigurable CMOS power amplifier for 3GPP LTE applications

Wide-band receiver architecture with flexible blocker filtering techniques

A cost effective RF-SOI Drain Extended MOS transistor featuring PSAT=19dBm @28GHz & VDD=3V for 5G Power Amplifier application

2.2 V 300 mu A RDS pager baseband decoder

The first experimental demonstration of a SASP-based full Software Radio receiver

A 12.7dBm IIP3, 1.34dB NF, 4.9GHz–5.9GHz 802.11a/n LNA in 0.13 µm PD-SOI CMOS with Body-Contacted transistor

Activity profiling: Review of different solutions to develop reliable and performant design

A highly linear and tunable feed forward current source active inductor in 65nm CMOS technology for mobile applications

From Software-Defined to Software Radio: Analog Signal Processor features

65nm CMOS Circuit design of a sampled analog signal processor dedicated to RF applications

A 2.2 V 300 /spl mu/A RDS pager baseband decoder

A fully-integrated CMOS AM radio receiver for wrist-watch calibration

Fragmentation in spin ice from magnetic charge injection

Nanoscale CMOS Transceiver Design in the 90-170-GHz Range

A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3% DC-to-RF Efficiency, and 1-GHz Divided-Down Output

Impact of Aging Degradation on Heavy-Ion SEU Response of 28-nm UTBB FD-SOI Technology

Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR

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