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Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-10, Vol.43 (10), p.3083-3087

2024

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Improving Bounded Model Checking Exploiting Interpolation-Based Learning and Strengthening

IEEE access, 2024, Vol.12, p.119341-119349

2024

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Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, p.1122-1125

2021

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Correct Hardware Design and Verification Methods: IFIP WG 10.5 Advanced Research Working Conference, CHARME '95 Frankfurt/Main, Germany, October 2–4, 1995 Proceedings

1995

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Hardware Model Checking Algorithms and Techniques

Algorithms, 2024-06, Vol.17 (6), p.253

2024

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Comparative analysis of models and performance indicators for optimal service facility location

Transportation research. Part E, Logistics and transportation review, 2021-01, Vol.145, p.102174, Article 102174

2021

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A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties

Software, practice & experience, 2016-04, Vol.46 (4), p.493-511

2016

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A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties: A GRAPH-LABELING APPROACH FOR EFFICIENT CONE-OF-INFLUENCE COMPUTATION

Software, practice & experience, 2016-04, Vol.46 (4), p.493-511

2016

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KPIs for Optimal Location of charging stations for Electric Vehicles: the Biella case-study

2019 Federated Conference on Computer Science and Information Systems (FedCSIS), 2019, p.123-126

2019

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Model-Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification

Electronics (Basel), 2019-09, Vol.8 (9), p.1057

2019

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Evaluation of Optimal Charging Station Location for Electric Vehicles: An Italian Case-Study

Recent Advances in Computational Optimization, 2021, Vol.920, p.71-87

2021

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A Smart Many-Core Implementation of a Motion Planning Framework along a Reference Path for Autonomous Cars

Electronics (Basel), 2019-02, Vol.8 (2), p.177

2019

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Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification

Codes, Cryptology and Information Security, p.462-479

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Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper)

Software Engineering and Formal Methods, 2017, Vol.10469, p.382-387

2017

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Can BDDs compete with SAT solvers on bounded model checking?

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.117-122

2002

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Improving symbolic traversals by means of activity profiles

Proceedings - ACM IEEE Design Automation Conference, 1999, p.306-311

1999

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Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits

Annual ACM IEEE Design Automation Conference: Proceedings of the 34th annual conference on Design automation; 09-13 June 1997, 1997, p.728-733

1997

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Improved probabilistic verification by hash compaction

Correct Hardware Design and Verification Methods, 1995, p.206-224

1995

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Advancements in symbolic traversal techniques

Correct Hardware Design and Verification Methods, 2005, p.155-166

2005

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Improving symbolic reachability analysis by means of activity profiles

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-09, Vol.19 (9), p.1065-1075

2000

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Timing analysis of asynchronous circuits using timed automata

Correct Hardware Design and Verification Methods, 1995, p.189-205

1995

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Improving the efficiency of BDD-based operators by means of partitioning

IEEE transactions on computer-aided design of integrated circuits and systems, 1999, Vol.18 (5), p.545-556

1999

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Formal design of a class of computers — its high stage: abstract microprogramming

Correct Hardware Design and Verification Methods, 2005, p.84-102

2005

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A methodology for system-level design for verifiability

Correct Hardware Design and Verification Methods, 2005, p.80-91

2005

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Symbolic forward/backward traversals of large finite state machines

Journal of systems architecture, 2000-10, Vol.46 (12), p.1137-1158

2000

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Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification

Improving Bounded Model Checking Exploiting Interpolation-Based Learning and Strengthening

Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification

Correct Hardware Design and Verification Methods: IFIP WG 10.5 Advanced Research Working Conference, CHARME '95 Frankfurt/Main, Germany, October 2–4, 1995 Proceedings

Hardware Model Checking Algorithms and Techniques

Comparative analysis of models and performance indicators for optimal service facility location

A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties

A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties: A GRAPH-LABELING APPROACH FOR EFFICIENT CONE-OF-INFLUENCE COMPUTATION

KPIs for Optimal Location of charging stations for Electric Vehicles: the Biella case-study

Model-Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification

Evaluation of Optimal Charging Station Location for Electric Vehicles: An Italian Case-Study

A Smart Many-Core Implementation of a Motion Planning Framework along a Reference Path for Autonomous Cars

Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification

Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper)

Can BDDs compete with SAT solvers on bounded model checking?

Improving symbolic traversals by means of activity profiles

Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits

Improved probabilistic verification by hash compaction

Advancements in symbolic traversal techniques

Improving symbolic reachability analysis by means of activity profiles

Timing analysis of asynchronous circuits using timed automata

Improving the efficiency of BDD-based operators by means of partitioning

Formal design of a class of computers — its high stage: abstract microprogramming

A methodology for system-level design for verifiability

Symbolic forward/backward traversals of large finite state machines

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