UB Paderborn / Katalog / Suche / in CDI

Compact Rayleigh and Rician fading simulator based on random walk processes

IET communications, 2009-08, Vol.3 (8), p.1333-1342

2009

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Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

IEEE transactions on signal processing, 2004-05, Vol.52 (5), p.1315-1326

2004

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Accurate multiple-input multiple-output fading channel simulator using a compact and high-throughput reconfigurable architecture

IET communications, 2011-04, Vol.5 (6), p.844-852

2011

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Improved layered MIMO detection algorithm with near-optimal performance

Electronics letters, 2009, Vol.45 (13), p.675-677

2009

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Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models

IET communications, 2011-06, Vol.5 (9), p.1246-1254

2011

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Layered space-time multiple-input multiple-output detector with parameterisable performance

IET communications, 2012-11, Vol.6 (17), p.3053-3058

2012

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Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-12, Vol.53 (12), p.2595-2605

2006

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Voiceband signal classification using statistically optimal combinations of low-complexity discriminant variables

IEEE transactions on communications, 1999-11, Vol.47 (11), p.1623-1627

1999

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Efficient implementation of lifting-based discrete wavelet transform

Electronics letters, 2002-08, Vol.38 (18), p.1010-1012

2002

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Modeling and Hardware Implementation Aspects of Fading Channel Simulators

IEEE transactions on vehicular technology, 2008-07, Vol.57 (4), p.2055-2069

2008

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A Compact and Accurate Gaussian Variate Generator

IEEE transactions on very large scale integration (VLSI) systems, 2008-05, Vol.16 (5), p.517-527

2008

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An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading

IEEE transactions on vehicular technology, 2010-07, Vol.59 (6), p.2725-2734

2010

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Hardware Implementation of Nakagami and Weibull Variate Generators

IEEE transactions on very large scale integration (VLSI) systems, 2012-07, Vol.20 (7), p.1276-1284

2012

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Design of a 3-D fully depleted SOI computational RAM

IEEE transactions on very large scale integration (VLSI) systems, 2005-03, Vol.13 (3), p.358-369

2005

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Reconfigurable performance measurement system-on-a-chip for baseband wireless algorithm design and verification

IEEE wireless communications, 2012-12, Vol.19 (6), p.84-91

2012

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Deterministic tests for detecting single V-coupling faults in RAMs

Journal of electronic testing, 1994-02, Vol.5 (1), p.91-113

Cockburn, J

1994

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Hardware Implementation of Rayleigh and Ricean Variate Generators

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1495-1499

2011

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Design and Characterization of a Multilevel DRAM

IEEE transactions on very large scale integration (VLSI) systems, 2011-09, Vol.19 (9), p.1583-1596

2011

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Accurate simulation of non-isotropic fading channels with arbitrary temporal correlation

IET communications, 2012-03, Vol.6 (5), p.557

2012

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Improved layered MIMO detection algorithm with near-optimal performance

Electronics letters, 2009-06, Vol.45 (13), p.1-1

2009

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A Compact Single-FPGA Fading-Channel Simulator

IEEE transactions on circuits and systems. II, Express briefs, 2008-01, Vol.55 (1), p.84-88

2008

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An investigation into crosstalk noise in DRAM structures

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), 2002, p.123-129

2002

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Tutorial on semiconductor memory testing

Journal of electronic testing, 1994-11, Vol.5 (4), p.321-336

Cockburn, B. F.

1994

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Design and Test of a 175-Mb/s, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder

IEEE journal of solid-state circuits, 2007-10, Vol.42 (10), p.2245-2256

2007

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Panel on advanced embedded memory technologies

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), 2002, p.177-177

Cockburn, B.F.

2002

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Compact Rayleigh and Rician fading simulator based on random walk processes

Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

Accurate multiple-input multiple-output fading channel simulator using a compact and high-throughput reconfigurable architecture

Improved layered MIMO detection algorithm with near-optimal performance

Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models

Layered space-time multiple-input multiple-output detector with parameterisable performance

Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density

Voiceband signal classification using statistically optimal combinations of low-complexity discriminant variables

Efficient implementation of lifting-based discrete wavelet transform

Modeling and Hardware Implementation Aspects of Fading Channel Simulators

A Compact and Accurate Gaussian Variate Generator

An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading

Hardware Implementation of Nakagami and Weibull Variate Generators

Design of a 3-D fully depleted SOI computational RAM

Reconfigurable performance measurement system-on-a-chip for baseband wireless algorithm design and verification

Deterministic tests for detecting single V-coupling faults in RAMs

Hardware Implementation of Rayleigh and Ricean Variate Generators

Design and Characterization of a Multilevel DRAM

Accurate simulation of non-isotropic fading channels with arbitrary temporal correlation

Improved layered MIMO detection algorithm with near-optimal performance

A Compact Single-FPGA Fading-Channel Simulator

An investigation into crosstalk noise in DRAM structures

Tutorial on semiconductor memory testing

Design and Test of a 175-Mb/s, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder

Panel on advanced embedded memory technologies

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