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Analysis and Optimization of Four-Coil Planar Magnetically Coupled Printed Spiral Resonators

Sensors (Basel, Switzerland), 2016-08, Vol.16 (8), p.1219-1219

2016

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A Fully Digital Background Calibration Technique for M-Channel Time-Interleaved ADCs

Circuits, systems, and signal processing, 2017-08, Vol.36 (8), p.3303-3319

2017

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An optimized framework for degree distribution in LT codes based on power law

Journal of Central South University, 2013-10, Vol.20 (10), p.2693-2699

2013

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Single front-end SOC for accessing CD/DVD/BD with maximum speed

IEEE transactions on consumer electronics, 2009-05, Vol.55 (2), p.792-799

2009

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A current mode equalizer for an optical disc front-end

IEEE transactions on consumer electronics, 2009-05, Vol.55 (2), p.564-569

2009

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Performance of M-QAM, M-DPSK and M-PSK with MRC diversity in a Nakagami-m fading channel

Journal of Central South University, 2014-04, Vol.21 (4), p.1347-1352

2014

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Performance analysis of orthogonal space-time codes applicable to 4G LTE communications

2015 International Symposium on Consumer Electronics (ISCE), 2015, p.1-2

2015

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Power and area-optimised Carry-Select Adder architecture for standard cell-based design

International journal of electronics, 2015-08, Vol.102 (8), p.1348-1360

2015

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Optimization of planar strongly coupled wireless power transfer system for biomedical applications

Microwave and optical technology letters, 2016-08, Vol.58 (8), p.1861-1866

2016

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Improved Belief Propagation Decoding Algorithm for Short Polar Codes

Wireless personal communications, 2017-09, Vol.96 (1), p.1437-1449

2017

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Design and implementation of a novel LT codec architecture on TTA based codesign environment

IEICE Electronics Express, 2016, Vol.13 (13), p.20160298-20160298

2016

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Low-power and area-efficient 9-transistor double-edge triggered flip-flop

IEICE Electronics Express, 2013-01, Vol.10 (18), p.20130639-20130639

2013

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Response of transport triggered architectures for high-speed processor design

IEICE Electronics Express, 2013-01, Vol.10 (5), p.20120878-20120878

2013

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Design and implementation of LT codec architecture with optimized degree distribution

IEICE Electronics Express, 2013-01, Vol.10 (12), p.20130340-20130340

2013

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A DPLL with a Modified Phase Frequency Detector to Reduce Lock Time

Journal of the Institute of Electronics and Information Engineers, 2013-10, Vol.50 (10), p.76-81

2013

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Performance evaluation of novel degree distribution on power law of LT codes for internet technology

2015 International Symposium on Consumer Electronics (ISCE), 2015, p.1-2

2015

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High-efficiency CMOS rectifier with minimized leakage and threshold cancellation features for low power bio-implants

Microelectronics, 2017-08, Vol.66, p.67-75

2017

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Hardware feasible offset and gain error correction for time-interleaved ADC

2017 International SoC Design Conference (ISOCC), 2017, p.254-255

2017

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The Front-End LSI with a 5-Tap PRML for 2 x Reading and Writing of BD-R/RW/ROM

IEICE transactions on electronics, 2007-04, Vol.E90-C (4), p.727-730

2007

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Enhanced Belief Propagation Polar Decoder for Finite Lengths

Journal of the Korea Society of Digital Industry and Information Management, 2015-09, Vol.11 (3), p.45-51

2015

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A Custom Code Generation Technique for ASIPs from High-level Language

Journal of the Korea Society of Digital Industry and Information Management, 2015-09, Vol.11 (3), p.31-43

2015

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A 0.18 /spl mu/m CMOS SoC of a front-end hardware platform for DVD-multi recorders

2005 Digest of Technical Papers. International Conference on Consumer Electronics, 2005. ICCE, 2005, p.53-54

2005

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A 0.18 /spl mu/m CMOS front-end processor for a blu-ray disc recorder with an adaptive PRML

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.426-537 Vol.1

2004

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The front-end SOC for a Blu-ray disc recorder

IEEE communications magazine, 2004-12, Vol.42 (12), p.124-131

Choi, GoangSeog

2004

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A 0.18μm CMOS front-end processor for a blu-ray disc recorder with an adaptive PRML

First edition, 2004

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Analysis and Optimization of Four-Coil Planar Magnetically Coupled Printed Spiral Resonators

A Fully Digital Background Calibration Technique for M-Channel Time-Interleaved ADCs

An optimized framework for degree distribution in LT codes based on power law

Single front-end SOC for accessing CD/DVD/BD with maximum speed

A current mode equalizer for an optical disc front-end

Performance of M-QAM, M-DPSK and M-PSK with MRC diversity in a Nakagami-m fading channel

Performance analysis of orthogonal space-time codes applicable to 4G LTE communications

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

Optimization of planar strongly coupled wireless power transfer system for biomedical applications

Improved Belief Propagation Decoding Algorithm for Short Polar Codes

Design and implementation of a novel LT codec architecture on TTA based codesign environment

Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Response of transport triggered architectures for high-speed processor design

Design and implementation of LT codec architecture with optimized degree distribution

A DPLL with a Modified Phase Frequency Detector to Reduce Lock Time

Performance evaluation of novel degree distribution on power law of LT codes for internet technology

High-efficiency CMOS rectifier with minimized leakage and threshold cancellation features for low power bio-implants

Hardware feasible offset and gain error correction for time-interleaved ADC

The Front-End LSI with a 5-Tap PRML for 2 x Reading and Writing of BD-R/RW/ROM

Enhanced Belief Propagation Polar Decoder for Finite Lengths

A Custom Code Generation Technique for ASIPs from High-level Language

A 0.18 /spl mu/m CMOS SoC of a front-end hardware platform for DVD-multi recorders

A 0.18 /spl mu/m CMOS front-end processor for a blu-ray disc recorder with an adaptive PRML

The front-end SOC for a Blu-ray disc recorder

A 0.18μm CMOS front-end processor for a blu-ray disc recorder with an adaptive PRML

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