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Reliability aspects of gate oxide under ESD pulse stress

Microelectronics and reliability, 2009-12, Vol.49 (12), p.1407-1416

2009

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Optimized 750V SiC MOSFETs for Electric Vehicle Inverter Operation

Key engineering materials, 2023-05, Vol.945, p.67-70

2023

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Advanced SiC Power MOSFETs Manufactured on 150mm SiC Wafers

Materials Science Forum, 2016-05, Vol.858, p.803-806

2016

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Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies

2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.163-168

2006

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Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

Microelectronics and reliability, 2009-12, Vol.49 (12), p.1417-1423

2009

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Characterization of high-k/metal gate stack breakdown in the time scale of ESD events

2010 IEEE International Reliability Physics Symposium, 2010, p.846-852

2010

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1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

Materials science forum, 2014-02, Vol.778-780, p.903-906

2014

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1700V, 5.5mohm-cm super(2) 4H-SiC DMOSFET with Stable 225[degrees]C Operation

Materials science forum, 2014-02, Vol.778-780, p.903-906

2014

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Large scale test bed for in-circuit reliability testing of silicon carbide diodes and MOSFETs emulating real life voltage and current stress

2017 IEEE Applied Power Electronics Conference and Exposition (APEC), 2017, p.2282-2289

2017

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900V, 1.46mOhm-cm2 4H-SiC Depletion Mode Vertical JFET

Materials science forum, 2013-01, Vol.740-742, p.915-920

2013

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900V, 1.46mOhm-cm super(2) 4H-SiC Depletion Mode Vertical JFET

Materials science forum, 2013-01, Vol.740-742, p.915-920

2013

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Demonstration of SiC Vertical Trench JFET Reliability

Materials science forum, 2012, Vol.717-720, p.1017-1020

2012

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Reverse conduction properties of vertical SiC trench JFETs

2012 24th International Symposium on Power Semiconductor Devices and ICs, 2012, p.385-388

2012

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Reliability aspects of gate oxide under ESD pulse stress

2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2009, Vol.49 (12), p.6A.1-1-6A.1-10

2009

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Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.348-357

2007

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Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs

Microelectronics and reliability, 2007-07, Vol.47 (7), p.1030-1035

2007

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Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs

Microelectronics and reliability, 2007-07, Vol.47 (7), p.1069-1073

2007

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Design automation to suppress cable discharge event (CDE) induced latchup in 90nm CMOS ASICs

Microelectronics and reliability, 2007-07, Vol.47 (7), p.1069-1073

2007

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Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90nm CMOS ASICs

Microelectronics and reliability, 2007-07, Vol.47 (7), p.1030-1035

2007

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650V and 900V, 150A SiC Schottky diode for automotive applications

2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2016, p.143-146

2016

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Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2006, p.276-280

2006

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External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.358-363

2007

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Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.145-150

2006

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Reliability aspects of gate oxide under ESD pulse stress : Electrostatic Discharge Reliability

Microelectronics and reliability, 2009, Vol.49 (12), p.1407-1416

2009

Volltextzugriff (PDF)

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology : Electrostatic Discharge Reliability

Microelectronics and reliability, 2009, Vol.49 (12), p.1417-1423

2009

Volltextzugriff (PDF)

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Reliability aspects of gate oxide under ESD pulse stress

Optimized 750V SiC MOSFETs for Electric Vehicle Inverter Operation

Advanced SiC Power MOSFETs Manufactured on 150mm SiC Wafers

Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

Characterization of high-k/metal gate stack breakdown in the time scale of ESD events

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

1700V, 5.5mohm-cm super(2) 4H-SiC DMOSFET with Stable 225[degrees]C Operation

Large scale test bed for in-circuit reliability testing of silicon carbide diodes and MOSFETs emulating real life voltage and current stress

900V, 1.46mOhm-cm2 4H-SiC Depletion Mode Vertical JFET

900V, 1.46mOhm-cm super(2) 4H-SiC Depletion Mode Vertical JFET

Demonstration of SiC Vertical Trench JFET Reliability

Reverse conduction properties of vertical SiC trench JFETs

Reliability aspects of gate oxide under ESD pulse stress

Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs

Design automation to suppress cable discharge event (CDE) induced latchup in 90nm CMOS ASICs

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90nm CMOS ASICs

650V and 900V, 150A SiC Schottky diode for automotive applications

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

Reliability aspects of gate oxide under ESD pulse stress : Electrostatic Discharge Reliability

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology : Electrostatic Discharge Reliability

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