UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 161

Sortiert nach

An Energy-Efficient Equalized Transceiver for RC-Dominant Channels

IEEE journal of solid-state circuits, 2010-06, Vol.45 (6), p.1186-1197

2010

Volltextzugriff (PDF)

An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications

IEEE journal of solid-state circuits, 2018-02, Vol.53 (2), p.404-417

2018

Volltextzugriff (PDF)

Current-Mode Transceiver for Silicon Interposer Channel

IEEE journal of solid-state circuits, 2014-09, Vol.49 (9), p.2044-2053

2014

Volltextzugriff (PDF)

Impact of Line Mismatch on Two-Wire Deembedding Methods in Early Characterization of Emerging Interconnects

IEEE transactions on components, packaging, and manufacturing technology (2011), 2019-05, Vol.9 (5), p.905-912

2019

Volltextzugriff (PDF)

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3526-3538

2009

Volltextzugriff (PDF)

Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation

IEEE transactions on very large scale integration (VLSI) systems, 2017-06, Vol.25 (6), p.1821-1830

2017

Volltextzugriff (PDF)

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

IEEE journal of solid-state circuits, 2013-11, Vol.48 (11), p.2795-2804

2013

Volltextzugriff (PDF)

A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC

IEEE journal of solid-state circuits, 2016-02, Vol.51 (2), p.391-400

2016

Volltextzugriff (PDF)

An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects

IEEE transactions on circuits and systems. I, Regular papers, 2015-05, Vol.62 (5), p.1335-1344

2015

Volltextzugriff (PDF)

A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement

IEEE journal of solid-state circuits, 2016-08, Vol.51 (8), p.1902-1914

2016

Volltextzugriff (PDF)

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table

IEEE transactions on biomedical circuits and systems, 2018-02, Vol.12 (1), p.161-170

2018

Volltextzugriff (PDF)

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

IEEE transactions on circuits and systems. I, Regular papers, 2016-02, Vol.63 (2), p.276-287

2016

Volltextzugriff (PDF)

Investigation on the Worst Read Scenario of a ReRAM Crossbar Array

IEEE transactions on very large scale integration (VLSI) systems, 2017-09, Vol.25 (9), p.2402-2410

2017

Volltextzugriff (PDF)

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface

IEEE journal of solid-state circuits, 2014-11, Vol.49 (11), p.2618-2630

2014

Volltextzugriff (PDF)

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.144-154

2018

Volltextzugriff (PDF)

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors

IEEE transactions on biomedical circuits and systems, 2017-06, Vol.11 (3), p.523-533

2017

Volltextzugriff (PDF)

An Approximate Closed-Form Channel Model for Diverse Interconnect Applications

IEEE transactions on circuits and systems. I, Regular papers, 2014-10, Vol.61 (10), p.3034-3043

2014

Volltextzugriff (PDF)

A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation

IEEE transactions on biomedical circuits and systems, 2017-02, Vol.11 (1), p.87-97

2017

Volltextzugriff (PDF)

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs

IEEE transactions on circuits and systems. II, Express briefs, 2016-02, Vol.63 (2), p.141-145

2016

Volltextzugriff (PDF)

A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC

IEEE transactions on circuits and systems. I, Regular papers, 2017-07, Vol.64 (7), p.1706-1717

2017

Volltextzugriff (PDF)

An LCD-VCOM-Noise Resilient Mutual-Capacitive Touch-Sensor IC Chip With a Low-Voltage Driving Signal

IEEE sensors journal, 2015-08, Vol.15 (8), p.4595-4602

2015

Volltextzugriff (PDF)

A Body Channel Communication Technique Utilizing Decision Feedback Equalization

IEEE access, 2020, Vol.8, p.198468-198481

2020

Volltextzugriff (PDF)

All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.788-792

2017

Volltextzugriff (PDF)

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation

IEEE journal of solid-state circuits, 2013-09, Vol.48 (9), p.2118-2127

2013

Volltextzugriff (PDF)

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

IEEE transactions on circuits and systems. II, Express briefs, 2014-07, Vol.61 (7), p.481-485

2014

Volltextzugriff (PDF)

1 – 25 von 161

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(75)
Mit Volltextzugriff
(135)

Publikationsform

Sprache

Erscheinungsjahr

n.n

Thema

Science & Technology
(94)
Technology
(90)
Engineering
(89)
Engineering, Electrical & Electronic
(89)
Transceivers
(26)
Clocks
(25)
Computer Science
(22)
Cmos
(20)
Physical Sciences
(19)
Transmitters
(19)
Physics
(18)
Computer Science, Hardware & Architecture
(17)
Integrated Circuit Interconnections
(16)
Physics, Applied
(15)
Receivers
(15)
Circuits
(14)
Delays
(14)
Power Demand
(14)
Resistance
(14)
Decision Feedback Equalizers
(13)

15 weitere anzeigen...

Weniger anzeigen...

Kollektion

8 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

... seit 7 Tagen
(1)
... seit 90 Tagen
(3)

Menü

Weitere Dienste

Einstellungen

An Energy-Efficient Equalized Transceiver for RC-Dominant Channels

An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications

Current-Mode Transceiver for Silicon Interposer Channel

Impact of Line Mismatch on Two-Wire Deembedding Methods in Early Characterization of Emerging Interconnects

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC

An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects

A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

Investigation on the Worst Read Scenario of a ReRAM Crossbar Array

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors

An Approximate Closed-Form Channel Model for Diverse Interconnect Applications

A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs

A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC

An LCD-VCOM-Noise Resilient Mutual-Capacitive Touch-Sensor IC Chip With a Low-Voltage Driving Signal

A Body Channel Communication Technique Utilizing Decision Feedback Equalization

All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

Suchergebnisse filtern