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Enhanced write performance of a 64-mb phase-change random access memory

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.122-126

2006

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IEEE_Xplore

An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.823-830

2006

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IEEE_Xplore

Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM

ETRI Journal, 2010, 32(3), , pp.406-413

2010

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A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation

IEEE journal of solid-state circuits, 2007, Vol.42 (1), p.210-218

2007

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Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

ETRI Journal, 2005, 27(1), , pp.81-88

2005

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A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1943-1951

2003

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IEEE_Xplore

Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

ETRI journal, 2010-06, Vol.32 (3), p.406-413

2010

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Verfügbarkeit prüfen

Voltage‐Mode 1.5 Gbps Interface Circuits for Chip‐to‐Chip Communication

ETRI journal, 2005-02, Vol.27 (1), p.81-88

2005

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A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

IEEE journal of solid-state circuits, 2007-01, Vol.42 (1), p.210-218

2007

Link zum Volltext
IEEE_Xplore

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.386-622

2008

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IEEE_Xplore

Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.533-536

2005

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IEEE_Xplore

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1847-1850 Vol. 2

2005

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IEEE_Xplore

A pseudo-differential CMOS receiver insensitive to input common mode level

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.440-443 Vol. 1

2005

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IEEE_Xplore

A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops

2005 IEEE Asian Solid-State Circuits Conference, 2005, p.365-368

2005

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IEEE_Xplore

A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.498-542 Vol.1

First edition, 2004

Link zum Volltext
IEEE_Xplore

The effects of STI process parameters on the integrity of dual gate oxides

2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167), 2001, p.48-51

2001

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IEEE_Xplore

A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

IEEE journal of solid-state circuits, 2005, Vol.40 (1), p.293-300

2005

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An autonomous SRAM with on-chip sensors in an 80nm double stacked cell technology

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.232-235

2005

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IEEE_Xplore

A SRAM Core Architecture with Adaptive Cell Bias Scheme

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers, 2006, p.128-129

2006

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IEEE_Xplore

A 0.18-[micro]m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.293

2005

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A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.293-300

2005

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A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.293-300

2005

Link zum Volltext
IEEE_Xplore

A 0.18μm 3.0V 64Mb non-volatile phase-transition random-access memory (PRAM)

First edition, 2004

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Verfügbarkeit prüfen

Enhanced write performance of a 64 Mb phase-change random access memory

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.48-584 Vol. 1

2005

Link zum Volltext
IEEE_Xplore

A 0.1/spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.487-496

2006

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IEEE_Xplore

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Enhanced write performance of a 64-mb phase-change random access memory

An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM

A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation

Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

Voltage‐Mode 1.5 Gbps Interface Circuits for Chip‐to‐Chip Communication

A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

A pseudo-differential CMOS receiver insensitive to input common mode level

A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops

A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

The effects of STI process parameters on the integrity of dual gate oxides

A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

An autonomous SRAM with on-chip sensors in an 80nm double stacked cell technology

A SRAM Core Architecture with Adaptive Cell Bias Scheme

A 0.18-[micro]m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

A 0.18μm 3.0V 64Mb non-volatile phase-transition random-access memory (PRAM)

Enhanced write performance of a 64 Mb phase-change random access memory

A 0.1/spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM

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