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Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1116-1128

2013

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What we know after twelve years developing and deploying test data analytics solutions

2016 IEEE International Test Conference (ITC), 2016, p.1-8

2016

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Minimizing power consumption in scan testing: pattern generation and DFT techniques

2004 International Conferce on Test, 2004, p.355-364

2004

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Power Supply Noise: A Survey on Effects and Research

IEEE design & test of computers, 2010-03, Vol.27 (2), p.51-67

2010

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Physics-Based Low-Cost Test Technique for High Voltage LDMOS

Journal of electronic testing, 2013-12, Vol.29 (6), p.745-762

2013

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Scan-based transition fault testing - implementation and low cost test challenges

Proceedings - International Test Conference, 2002, p.1120-1129

2002

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Adapting to adaptive testing

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010, p.556-561

2010

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Local at-speed scan enable generation for transition fault testing using low-cost testers

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-05, Vol.26 (5), p.896-906

2007

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Efficient Process Shift Detection and Test Realignment

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-12, Vol.32 (12), p.1934-1942

2013

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Statistical outlier screening as a test solution health monitor

2016 IEEE International Test Conference (ITC), 2016, p.1-10

2016

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Accurate ADC testing with significantly relaxed instrumentation including large cumulative jitter

2017 IEEE International Test Conference (ITC), 2017, p.1-10

2017

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Facilitating rapid first silicon debug

Proceedings - International Test Conference, 2002, p.628-637

2002

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Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-05, Vol.26 (5), p.896-906

2007

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A case study of ir-drop in structured at-speed testing

International Test Conference, 2003. Proceedings. ITC 2003, 2003, Vol.1, p.1098-1104

2003

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Is ITC bored with board test?

Proceedings - International Test Conference, 2002, p.1237-1237

Butler, K.M.

2002

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Test data analytics - Exploring spatial and test-item correlations in production test data

2013 IEEE International Test Conference (ITC), 2013, p.1-10

2013

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A case study on the implementation of the Illinois Scan Architecture

Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001, p.538-547

2001

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A design-for-reliability approach based on grading library cells for aging effects

2013 IEEE International Test Conference (ITC), 2013, p.1-7

2013

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Adaptive test flow for mixed-signal/RF circuits using learned information from device under test

2010 IEEE International Test Conference, 2010, p.1-10

2010

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Adaptive multidimensional outlier analysis for analog and mixed signal circuits

2011 IEEE International Test Conference, 2011, p.1-8

2011

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Test cost reduction through performance prediction using virtual probe

2011 IEEE International Test Conference, 2011, p.1-9

2011

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Quality improvement and cost reduction using statistical outlier methods

2009 IEEE International Conference on Computer Design, 2009, p.64-69

2009

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At-speed structural test: Getting more real every day

2007 IEEE International Test Conference, 2007, p.1-1

Butler, K.M.

2007

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Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

2014 International Test Conference, 2014, p.1-10

2014

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An analysis of power reduction techniques in scan testing

Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001, p.670-677

2001

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Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring

What we know after twelve years developing and deploying test data analytics solutions

Minimizing power consumption in scan testing: pattern generation and DFT techniques

Power Supply Noise: A Survey on Effects and Research

Physics-Based Low-Cost Test Technique for High Voltage LDMOS

Scan-based transition fault testing - implementation and low cost test challenges

Adapting to adaptive testing

Local at-speed scan enable generation for transition fault testing using low-cost testers

Efficient Process Shift Detection and Test Realignment

Statistical outlier screening as a test solution health monitor

Accurate ADC testing with significantly relaxed instrumentation including large cumulative jitter

Facilitating rapid first silicon debug

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

A case study of ir-drop in structured at-speed testing

Is ITC bored with board test?

Test data analytics - Exploring spatial and test-item correlations in production test data

A case study on the implementation of the Illinois Scan Architecture

A design-for-reliability approach based on grading library cells for aging effects

Adaptive test flow for mixed-signal/RF circuits using learned information from device under test

Adaptive multidimensional outlier analysis for analog and mixed signal circuits

Test cost reduction through performance prediction using virtual probe

Quality improvement and cost reduction using statistical outlier methods

At-speed structural test: Getting more real every day

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

An analysis of power reduction techniques in scan testing

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