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Using simulation and satisfiability to compute flexibilities in Boolean networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-05, Vol.25 (5), p.743-755

2006

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Linear cofactor relationships in Boolean functions

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1011-1023

2006

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Sibling-substitution-based BDD minimization using don't cares

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-01, Vol.19 (1), p.44-55

2000

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Symbolic model checking for sequential circuit verification

IEEE transactions on computer-aided design of integrated circuits and systems, 1994-04, Vol.13 (4), p.401-424

1994

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Symbolic model checking : 1020 states and beyond

Information and computation, 1992-06, Vol.98 (2), p.142-170

1992

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Memory modeling in ESL-RTL equivalence checking

2007 44th ACM/IEEE Design Automation Conference, 2007, p.205-209

2007

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Techniques for verifying superscalar microprocessors

33rd Design Automation Conference Proceedings, 1996, 1996, p.552-557

Burch, J.R.

1996

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Safe BDD Minimization Using Don't Cares

Proceedings - ACM IEEE Design Automation Conference, 1997, p.208-213

1997

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Automatic verification of sequential control systems using temporal logic

AIChE journal, 1992-01, Vol.38 (1), p.67-75

1992

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The measurement of scratch

Burch, J.R

1992

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Tight integration of combinational verification methods

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287), 1998, p.570-576

1998

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Modelling timing assumption with trace theory

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1989, p.208-211

Burch, J.R.

1989

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Symbolic model checking: 10 20 States and beyond

Information and computation, 1992, Vol.98 (2), p.142-170

1992

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Delay models for verifying speed-dependent asynchronous circuits

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 1992, p.270-274

Burch, J.R.

1992

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Robust latch mapping for combinational equivalence checking

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287), 1998, p.563-569

1998

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Detecting support-reducing bound sets using two-cofactor symmetries

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005, 2005, Vol.1, p.266-271 Vol. 1

2005

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Opiates, sleep and itch

Clinical and experimental dermatology, 1988-11, Vol.13 (6), p.418-419

1988

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Using BDDs to verify multipliers

28th ACM/IEEE Design Automation Conference, 1991, p.408-412

Burch, Jerry R.

1991

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Sequential circuit verification using symbolic model checking

27th ACM/IEEE Design Automation Conference, 1990, p.46-51

1990

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Efficient validity checking for processor verification

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995, p.2-6

1995

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Sufficient conditions for correct gate-level speed-independent circuits

Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994, p.33-43

1994

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Representing circuits more efficiently in symbolic model checking

28th ACM/IEEE Design Automation Conference, 1991, p.403-407

1991

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Modeling hierarchical combinational circuits

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993, p.612-615

1993

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Symbolic model checking: 10/sup 20/ states and beyond

[1990] Proceedings. Fifth Annual IEEE Symposium on Logic in Computer Science, 1990, p.428-439

1990

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The long-lasting antidepressant effects of rapastinel (GLYX-13) are associated with a metaplasticity process in the medial prefrontal cortex and hippocampus

Neuroscience, 2015-11, Vol.308, p.202-211

2015

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Using simulation and satisfiability to compute flexibilities in Boolean networks

Linear cofactor relationships in Boolean functions

Sibling-substitution-based BDD minimization using don't cares

Symbolic model checking for sequential circuit verification

Symbolic model checking : 1020 states and beyond

Memory modeling in ESL-RTL equivalence checking

Techniques for verifying superscalar microprocessors

Safe BDD Minimization Using Don't Cares

Automatic verification of sequential control systems using temporal logic

The measurement of scratch

Tight integration of combinational verification methods

Modelling timing assumption with trace theory

Symbolic model checking: 10 20 States and beyond

Delay models for verifying speed-dependent asynchronous circuits

Robust latch mapping for combinational equivalence checking

Detecting support-reducing bound sets using two-cofactor symmetries

Opiates, sleep and itch

Using BDDs to verify multipliers

Sequential circuit verification using symbolic model checking

Efficient validity checking for processor verification

Sufficient conditions for correct gate-level speed-independent circuits

Representing circuits more efficiently in symbolic model checking

Modeling hierarchical combinational circuits

Symbolic model checking: 10/sup 20/ states and beyond

The long-lasting antidepressant effects of rapastinel (GLYX-13) are associated with a metaplasticity process in the medial prefrontal cortex and hippocampus

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