UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 51

Sortiert nach

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology

IEEE journal of solid-state circuits, 2022-11, Vol.57 (11), p.1-16

2022

Volltextzugriff (PDF)

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS

IEEE journal of solid-state circuits, 2020-03, Vol.55 (3), p.731-743

2020

Volltextzugriff (PDF)

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.19-26

2020

Volltextzugriff (PDF)

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.1214-1226

2018

Volltextzugriff (PDF)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1074-1086

2023

Volltextzugriff (PDF)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.3232-3248

2012

Volltextzugriff (PDF)

Errata - Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.1124-1124

2020

Volltextzugriff (PDF)

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.3220-3231

2012

Volltextzugriff (PDF)

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks

IEEE journal of solid-state circuits, 2015-12, Vol.50 (12), p.3120-3132

2015

Volltextzugriff (PDF)

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.863-874

2012

Volltextzugriff (PDF)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

IEEE journal of solid-state circuits, 2006-12, Vol.41 (12), p.2885-2900

2006

Volltextzugriff (PDF)

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2009-04, Vol.44 (4), p.1298-1305

2009

Volltextzugriff (PDF)

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.884-896

2012

Volltextzugriff (PDF)

A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.360-362

2022

Volltextzugriff (PDF)

Equalization for Electrical Links: Current Design Techniques and Future Directions

IEEE solid state circuits magazine, 2015, Vol.7 (4), p.23-31

Bulzacchelli, John F.

2015

Volltextzugriff (PDF)

Using Cryogenic CMOS Control Electronics to Enable a Two-Qubit Cross-Resonance Gate

PRX quantum, 2024-02, Vol.5 (1), p.010326, Article 010326

2024

Volltextzugriff (PDF)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2012-08, Vol.47 (8), p.1828-1841

2012

Volltextzugriff (PDF)

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

IEEE journal of solid-state circuits, 2007-04, Vol.42 (4), p.889-896

2007

Volltextzugriff (PDF)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.168-169

2022

Volltextzugriff (PDF)

A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.13-16

2022

Volltextzugriff (PDF)

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3526-3538

2009

Volltextzugriff (PDF)

Experimental demonstration of superconducting bandpass delta-sigma modulator

IEEE transactions on applied superconductivity, 2003-06, Vol.13 (2), p.471-476

2003

Volltextzugriff (PDF)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.10-23

2015

Volltextzugriff (PDF)

Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013, p.1-8

Bulzacchelli, John F.

2013

Volltextzugriff (PDF)

6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.122-124

2019

Volltextzugriff (PDF)

1 – 25 von 51

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(31)
Mit Volltextzugriff
(49)

Publikationsform

Artikel
(34)
Tagungsberichte
(17)

Sprache

Englisch
(51)
Japanisch
(5)

Erscheinungsjahr

n.n

Thema

Science & Technology
(30)
Engineering
(27)
Engineering, Electrical & Electronic
(27)
Technology
(27)
Clocks
(19)
Decision Feedback Equalizers
(17)
Receivers
(15)
Cmos
(14)
Bandwidth
(13)
Exact Sciences And Technology
(13)
Applied Sciences
(12)
Electronics
(12)
Transmitters
(12)
Integrated Circuits
(11)
Semiconductor Electronics. Microelectronics. Optoelectronics. Solid State Devices
(11)
Circuit Properties
(10)
Design. Technologies. Operation Analysis. Testing
(10)
Electric, Optical And Optoelectronic Circuits
(10)
Transceivers
(10)
Cmos Integrated Circuits
(9)

15 weitere anzeigen...

Weniger anzeigen...

Kollektion

2 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

Errata - Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology

Equalization for Electrical Links: Current Design Techniques and Future Directions

Using Cryogenic CMOS Control Electronics to Enable a Two-Qubit Cross-Resonance Gate

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS

A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

Experimental demonstration of superconducting bandpass delta-sigma modulator

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates

6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS

Suchergebnisse filtern