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Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

IEEE electron device letters, 2008-07, Vol.29 (7), p.791-794

2008

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Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

IEEE electron device letters, 2008-05, Vol.29 (5), p.518-521

2008

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Chip-Level Thermoelectric Power Generators Based on High-Density Silicon Nanowire Array Prepared With Top-Down CMOS Technology

IEEE electron device letters, 2011-05, Vol.32 (5), p.674-676

2011

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CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach

IEEE electron device letters, 2007-11, Vol.28 (11), p.1021-1024

2007

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Silicon nanowire sensor array using top–down CMOS technology

Sensors and actuators. A. Physical., 2008-07, Vol.145-146, p.207-213

2008

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Top-Down Silicon Nanowire-Based Thermoelectric Generator: Design and Characterization

Journal of electronic materials, 2012-06, Vol.41 (6), p.989-992

2012

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Effect of Electrical Contact Resistance in a Silicon Nanowire Thermoelectric Cooler and a Design Guideline for On-Chip Cooling Applications

Journal of electronic materials, 2013-07, Vol.42 (7), p.1476-1481

2013

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Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

Solid-state electronics, 2008-09, Vol.52 (9), p.1312-1317

2008

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Erratum to: Top-Down Silicon Nanowire-Based Thermoelectric Generator: Design and Characterization

Journal of electronic materials, 2012-06, Vol.41 (6), p.1858-1858

2012

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Silicon Nanowire Arrays for Label-Free Detection of DNA

Analytical chemistry (Washington), 2007-05, Vol.79 (9), p.3291-3297

2007

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Germanium-Rich SiGe Nanowires Formed Through Oxidation of Patterned SiGe FINs on Insulator

Journal of electronic materials, 2009-03, Vol.38 (3), p.443-448

2009

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Si, SiGe Nanowire Devices by Top-Down Technology and Their Applications

IEEE transactions on electron devices, 2008-11, Vol.55 (11), p.3107-3118

2008

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Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Journal of nanotechnology, 2012-01, Vol.2012 (2012), p.1-21

2012

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Highly sensitive measurements of PNA-DNA hybridization using oxide-etched silicon nanowire biosensors

Biosensors & bioelectronics, 2008-06, Vol.23 (11), p.1701-1707

2008

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Improved Vertical Silicon Nanowire Based Thermoelectric Power Generator With Polyimide Filling

IEEE electron device letters, 2012-05, Vol.33 (5), p.715-717

2012

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A comparative study of the transfusion effect of single donor apheresis platelets versus random donor platelets in the management of severe dengue infection in children

International Journal of Contemporary Pediatrics, 2022-05, Vol.9 (6), p.595

2022

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Progressive Development of Superjunction Power MOSFET Devices

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.211-219

2008

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Demographic, clinical, chest X-ray characteristics, and outcome of children admitted with acute bronchiolitis in the tertiary care hospital South India

Indian journal of child health, 2022-07, Vol.9 (6), p.99-101

Buddharaju, Chandradeve Varma B S K

2022

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Si, SiGe Nanowire Devices by TopaDown Technology and Their Applications

IEEE transactions on electron devices, 2008-01, Vol.55 (11)

2008

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Silicon nanowires thermoelectric devices

2010 Conference Proceedings IPEC, 2010, p.1181-1185

2010

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Si Nanowire CMOS Transistors and Circuits by Top-Down Technology Approach

ECS transactions, 2008, Vol.13 (1), p.201-211

2008

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Gate-All-Around Silicon Nanowire Devices: Are These the Future of CMOS?

ECS transactions, 2009, Vol.16 (10), p.729-729

2009

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Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007, p.303-306

2007

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CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs

ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008, p.318-321

2008

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Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

2007 IEEE International Electron Devices Meeting, 2007, p.79-82

2007

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Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

Chip-Level Thermoelectric Power Generators Based on High-Density Silicon Nanowire Array Prepared With Top-Down CMOS Technology

CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach

Silicon nanowire sensor array using top–down CMOS technology

Top-Down Silicon Nanowire-Based Thermoelectric Generator: Design and Characterization

Effect of Electrical Contact Resistance in a Silicon Nanowire Thermoelectric Cooler and a Design Guideline for On-Chip Cooling Applications

Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

Erratum to: Top-Down Silicon Nanowire-Based Thermoelectric Generator: Design and Characterization

Silicon Nanowire Arrays for Label-Free Detection of DNA

Germanium-Rich SiGe Nanowires Formed Through Oxidation of Patterned SiGe FINs on Insulator

Si, SiGe Nanowire Devices by Top-Down Technology and Their Applications

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Highly sensitive measurements of PNA-DNA hybridization using oxide-etched silicon nanowire biosensors

Improved Vertical Silicon Nanowire Based Thermoelectric Power Generator With Polyimide Filling

A comparative study of the transfusion effect of single donor apheresis platelets versus random donor platelets in the management of severe dengue infection in children

Progressive Development of Superjunction Power MOSFET Devices

Demographic, clinical, chest X-ray characteristics, and outcome of children admitted with acute bronchiolitis in the tertiary care hospital South India

Si, SiGe Nanowire Devices by TopaDown Technology and Their Applications

Silicon nanowires thermoelectric devices

Si Nanowire CMOS Transistors and Circuits by Top-Down Technology Approach

Gate-All-Around Silicon Nanowire Devices: Are These the Future of CMOS?

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs

Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

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