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Scalable communication architecture for network-attached accelerators

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, p.627-638

2015

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A Hierarchical Synchronized Data Acquisition Network for CBM

IEEE transactions on nuclear science, 2013-10, Vol.60 (5), p.3654-3660

2013

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Automatic and Transparent Resource Contention Mitigation for Improving Large-Scale Parallel File System Performance

2017 IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS), 2017, p.604-613

2017

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A Unified DAQ Interconnection Network With Precise Time Synchronization

IEEE transactions on nuclear science, 2010-04, Vol.57 (2), p.412-418

2010

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Communication Models for Distributed Intel Xeon Phi Coprocessors

2015 IEEE 21st International Conference on Parallel and Distributed Systems (ICPADS), 2015, p.499-506

2015

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Using Balanced Data Placement to Address I/O Contention in Production Environments

2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2016, p.9-17

2016

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TCCluster: A Cluster Architecture Utilizing the Processor Host Interface as a Network Interconnect

2010 IEEE International Conference on Cluster Computing, 2010, p.9-18

2010

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A HyperTransport 3 Physical Layer Interface for FPGAs

Reconfigurable Computing: Architectures, Tools and Applications, p.4-14

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VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers

2008 37th International Conference on Parallel Processing, 2008, p.238-245

2008

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An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

2012 IEEE Radio Frequency Integrated Circuits Symposium, 2012, p.109-112

2012

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Parallelrechner: Architekturen - Systeme - Werkzeuge

1995 edition., 2013

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High Performance Networks

Euro-Par 2010 - Parallel Processing, p.412-412

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On Achieving High Message Rates

2013 13th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing, 2013, p.498-505

2013

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Parallelrechner: Architekturen -- Systeme -- Werkzeuge

1, 1995

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A versatile, low latency HyperTransport core

International Symposium on Field Programmable Gate Arrays: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays; 18-20 Feb. 2007, 2007, p.45-52

2007

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High speed interface for digital centric transmitters

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2013, p.233-236

2013

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A unified interconnection network with precise time synchronization for the CBM DAQ-system

2009 16th IEEE-NPSS Real Time Conference, 2009, p.506-511

2009

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Efficient Virtualization of High-Performance Network Interfaces

2009 Eighth International Conference on Networks, 2009, p.434-439

2009

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An FPGA-Based Custom High Performance Interconnection Network

2009 International Conference on Reconfigurable Computing and FPGAs, 2009, p.113-118

2009

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An FPGA based verification platform for HyperTransport 3.x

2009 International Conference on Field Programmable Logic and Applications, 2009, p.631-634

2009

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Systeme für eine hocheffiziente elektrische und optische Kurzstreckenübertragung im SAN-Bereich (Systems for High-Efficient Electrical and Optical Short-Distance Data Transmission in System-Area-Networks)

Information technology (Munich, Germany), 2003-02, Vol.45 (2), p.65-71

2003

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Systeme für eine hocheffiziente elektrische und optische Kurzstreckenübertragung im SAN-Bereich (Systems for High-Efficient Electrical and Optical Short-Distance Data Transmission in System-Area-Networks): Systems for High-Efficient Electrical and Optical Short-Distance Data Transmission in System-Area-Networks

Information technology (Munich, Germany), 2003-02, Vol.45 (2), p.65-71

2003

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Introduction

Euro-Par 2011 Parallel Processing, p.263-263

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Inactivation of the Fto gene protects from obesity

Nature, 2009-04, Vol.458 (7240), p.894-898

2009

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A link between FTO, ghrelin, and impaired brain food-cue responsivity

The Journal of clinical investigation, 2013-08, Vol.123 (8), p.3539-3551

2013

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Scalable communication architecture for network-attached accelerators

A Hierarchical Synchronized Data Acquisition Network for CBM

Automatic and Transparent Resource Contention Mitigation for Improving Large-Scale Parallel File System Performance

A Unified DAQ Interconnection Network With Precise Time Synchronization

Communication Models for Distributed Intel Xeon Phi Coprocessors

Using Balanced Data Placement to Address I/O Contention in Production Environments

TCCluster: A Cluster Architecture Utilizing the Processor Host Interface as a Network Interconnect

A HyperTransport 3 Physical Layer Interface for FPGAs

VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers

An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

Parallelrechner: Architekturen - Systeme - Werkzeuge

High Performance Networks

On Achieving High Message Rates

Parallelrechner: Architekturen -- Systeme -- Werkzeuge

A versatile, low latency HyperTransport core

High speed interface for digital centric transmitters

A unified interconnection network with precise time synchronization for the CBM DAQ-system

Efficient Virtualization of High-Performance Network Interfaces

An FPGA-Based Custom High Performance Interconnection Network

An FPGA based verification platform for HyperTransport 3.x

Systeme für eine hocheffiziente elektrische und optische Kurzstreckenübertragung im SAN-Bereich (Systems for High-Efficient Electrical and Optical Short-Distance Data Transmission in System-Area-Networks)

Introduction

Inactivation of the Fto gene protects from obesity

A link between FTO, ghrelin, and impaired brain food-cue responsivity

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