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Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications

IEEE transactions on electron devices, 2002-02, Vol.49 (2), p.308-313

2002

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Threshold voltage roll-up/roll-off characteristic control in sub-0.2-[mu]m single workfunction gate CMOS for high-performance DRAM applications

IEEE transactions on electron devices, 2002-02, Vol.49 (2), p.308

2002

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Threshold voltage roll-up/roll-off characteristic control in sub-0.2-/spl mu/m single workfunction gate CMOS for high-performance DRAM applications

IEEE transactions on electron devices, 2002-02, Vol.49 (2), p.308-313

2002

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A 4-Mb low-temperature DRAM

IEEE journal of solid-state circuits, 1991-11, Vol.26 (11), p.1519-1529

1991

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A Novel Trench Capacitor Structure for ULSI DRAMs

1991 Symposium on VLSI Technology, 1991, p.7-8

1991

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A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

IEEE journal of solid-state circuits, 1989-10, Vol.24 (5), p.1198-1205

1989

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Characterization of transient process phenomena using a temperature-tolerant metallurgy

IEEE electron device letters, 1984-03, Vol.5 (3), p.75-77

1984

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Characteristics of vertical p-channel MOSFETs for high density circuit application

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, 1991, p.376-379

1991

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A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216), 1998, p.36-37

1998

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A Fully Planarized 0.25 /spl mu/m CMOS Technology

1991 Symposium on VLSI Technology, 1991, p.83-84

1991

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A buried-trench DRAM cell using a self-aligned epitaxy over trench technology

Technical Digest., International Electron Devices Meeting, 1988, p.588-591

1988

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Trench storage capacitors for high density DRAMs

International Electron Devices Meeting 1991 [Technical Digest], 1991, p.835-838

1991

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A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999, p.25-28

1999

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A 4 Mb Low-temperature DRAM

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1991, p.30-31

1991

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The evolution of DRAM cell technology

Solid state technology, 1997-05, Vol.40 (5), p.89

1997

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Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications

Threshold voltage roll-up/roll-off characteristic control in sub-0.2-[mu]m single workfunction gate CMOS for high-performance DRAM applications

Threshold voltage roll-up/roll-off characteristic control in sub-0.2-/spl mu/m single workfunction gate CMOS for high-performance DRAM applications

A 4-Mb low-temperature DRAM

A Novel Trench Capacitor Structure for ULSI DRAMs

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Characterization of transient process phenomena using a temperature-tolerant metallurgy

Characteristics of vertical p-channel MOSFETs for high density circuit application

A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM

A Fully Planarized 0.25 /spl mu/m CMOS Technology

A buried-trench DRAM cell using a self-aligned epitaxy over trench technology

Trench storage capacitors for high density DRAMs

A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

A 4 Mb Low-temperature DRAM

The evolution of DRAM cell technology

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