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Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2007-11, Vol.25 (6), p.2030-2033

2007

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Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

Semiconductor science and technology, 2010-04, Vol.25 (4), p.045014-045014

2010

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Hybrid high resolution lithography (e-beam/deep ultraviolet) and etch process for the fabrication of stacked nanowire metal oxide semiconductor field effect transistors

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2008-11, Vol.26 (6), p.2583-2586

2008

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Performance of Localized-SOI MOS Devices on (110) Substrates: Impact of Channel Direction

IEEE electron device letters, 2011-08, Vol.32 (8), p.996-998

2011

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IEEE_Xplore

Influence of induced stress on enrichment kinetic during local Ge condensation of SiGe/SOI mesas

Thin solid films, 2010, Vol.518 (6), p.S92-S95

2010

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Investigation of charge-trap memories with AlN based band engineered storage layers

Solid-state electronics, 2011-04, Vol.58 (1), p.68-74

2011

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Through Silicon Via technology using tungsten metallization

2011 IEEE International Conference on IC Design & Technology, 2011, p.1-4

2011

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IEEE_Xplore

Acute thrombosis of limb arteries in horses with sepsis: five cases (1988–1998)

Equine veterinary journal, 2001-01, Vol.33 (1), p.105-109

2001

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Evaluation of HfAlO high- k materials for control dielectric applications in non-volatile memories

Microelectronic engineering, 2008-12, Vol.85 (12), p.2393-2399

2008

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WITHDRAWN: Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration

Microelectronic engineering, 2020-05, p.111336, Article 111336

2020

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Metallic colour filtering arrays manufactured by Nanolmprint lithography

Microelectronic engineering, 2013-11, Vol.111, p.193-198

2013

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Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- [Formula Omitted] Control Dielectrics

IEEE transactions on electron devices, 2012-04, Vol.59 (4), p.933

2012

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Passivated TiN nanocrystals/SiN trapping layer for enhanced erasingin nonvolatile memory

Applied physics letters, 2010-10, Vol.97 (15), p.152112-152112-3

2010

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A canine model of cutaneous late‐phase reactions: prednisolone inhibition of cellular and cytokine responses

Immunology, 2006-02, Vol.117 (2), p.177-187

2006

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Large-Scale Integration of Nanoelectromechanical Systems for Gas Sensing Applications

Metallic colour filtering arrays manufactured by NanoImprint lithography

Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration

Silicon solar cells efficiency improvement with Nano Imprint Lithography technology

Passivated TiN nanocrystals/SiN trapping layer for enhanced erasing in nonvolatile memory

Improvement of high resolution lithography by using amorphous carbon hard mask

Reliability of charge trapping memories with high- k control dielectrics (Invited Paper)

Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- k Control Dielectrics

Intravenous Lidocaine and Small-Intestinal Size, Abdominal Fluid, and Outcome after Colic Surgery in Horses

Ultra-dense silicon nanowires: A technology, transport and interfaces challenges insight (invited)

Intravenous Lidocaine and Small-Intestinal Size, Abdominal Fluid, and Outcome after Colic Surgery in Horses

Sub- 30 ‐ nm hybrid lithography (electron beam∕deep ultraviolet) and etch process for fully depleted metal oxide semiconductor transistors

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

Hybrid high resolution lithography (e-beam/deep ultraviolet) and etch process for the fabrication of stacked nanowire metal oxide semiconductor field effect transistors

Performance of Localized-SOI MOS Devices on (110) Substrates: Impact of Channel Direction

Influence of induced stress on enrichment kinetic during local Ge condensation of SiGe/SOI mesas

Investigation of charge-trap memories with AlN based band engineered storage layers

Through Silicon Via technology using tungsten metallization

Acute thrombosis of limb arteries in horses with sepsis: five cases (1988–1998)

Evaluation of HfAlO high- k materials for control dielectric applications in non-volatile memories

WITHDRAWN: Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration

Metallic colour filtering arrays manufactured by Nanolmprint lithography

Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- [Formula Omitted] Control Dielectrics

Passivated TiN nanocrystals/SiN trapping layer for enhanced erasingin nonvolatile memory

A canine model of cutaneous late‐phase reactions: prednisolone inhibition of cellular and cytokine responses

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