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Reducing Structural Bias in Technology Mapping

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-12, Vol.25 (12), p.2894-2903

2006

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Retiming and Resynthesis: A Complexity Perspective

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-12, Vol.25 (12), p.2674-2686

2006

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A Simulation-Guided Paradigm for Logic Synthesis and Verification

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-08, Vol.41 (8), p.2573-2586

2022

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Verification and Synthesis of Clock-Gated Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-02, Vol.38 (2), p.366-379

2019

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2QBF: Challenges and Solutions

Theory and Applications of Satisfiability Testing – SAT 2016, p.453-469

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Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT

Theory and Applications of Satisfiability Testing – SAT 2016, p.212-227

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Automating Logic Transformations With Approximate SPFDs

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-05, Vol.30 (5), p.651-664

2011

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Sequential equivalence checking of clock-gated circuits

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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SAT-Based Complete Don't-Care Computation for Network Optimization

Design, Automation and Test in Europe, 2005, p.412-417

2005

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Improvements to Technology Mapping for LUT-Based FPGAs

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-02, Vol.26 (2), p.240-253

2007

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Planning for performance

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.122-127

1998

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Novel VLSI layout fabric for deep sub-micron applications

Proceedings - ACM IEEE Design Automation Conference, 1999

1999

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Delay-optimal technology mapping by DAG covering

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.348-351

1998

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Functional Dependency for Verification Reduction

Computer Aided Verification, 2004, p.268-280

2004

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High performance BDD package by exploiting memory hierarchy

Annual ACM IEEE Design Automation Conference: Proceedings of the 33rd annual conference on Design automation; 03-07 June 1996, 1996, p.635-640

1996

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Practical exact synthesis

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, p.309-314

2018

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Scalable progress verification in credit-based flow-control systems

Proceedings of the Conference on Design, Automation and Test in Europe, 2012, p.905-910

2012

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Implementation and use of SPFDs in optimizing Boolean networks

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287), 1998, p.103-110

1998

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Negative thinking in branch-and-bound: the case of unate covering

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-03, Vol.19 (3), p.281-294

2000

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Area and search space control for technology mapping

Proceedings - ACM IEEE Design Automation Conference, 2000-01

2000

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Retiming for DSM with area-delay trade-offs and delay constraints

Proceedings - ACM IEEE Design Automation Conference, 1999, p.725-730

1999

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Hierarchical functional timing analysis

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.580-585

1998

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Bi-Decomposition Using Boolean Relations

2015 Euromicro Conference on Digital System Design, 2015, p.72-78

2015

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A timing-driven module-based chip design flow

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.67-70

2004

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Logic operations are properties of computer-simulated interactions between excitable dendritic spines

Neuroscience, 1987-04, Vol.21 (1), p.151-165

1987

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Reducing Structural Bias in Technology Mapping

Retiming and Resynthesis: A Complexity Perspective

A Simulation-Guided Paradigm for Logic Synthesis and Verification

Verification and Synthesis of Clock-Gated Circuits

2QBF: Challenges and Solutions

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT

Automating Logic Transformations With Approximate SPFDs

Sequential equivalence checking of clock-gated circuits

SAT-Based Complete Don't-Care Computation for Network Optimization

Improvements to Technology Mapping for LUT-Based FPGAs

Planning for performance

Novel VLSI layout fabric for deep sub-micron applications

Delay-optimal technology mapping by DAG covering

Functional Dependency for Verification Reduction

High performance BDD package by exploiting memory hierarchy

Practical exact synthesis

Scalable progress verification in credit-based flow-control systems

Implementation and use of SPFDs in optimizing Boolean networks

Negative thinking in branch-and-bound: the case of unate covering

Area and search space control for technology mapping

Retiming for DSM with area-delay trade-offs and delay constraints

Hierarchical functional timing analysis

Bi-Decomposition Using Boolean Relations

A timing-driven module-based chip design flow

Logic operations are properties of computer-simulated interactions between excitable dendritic spines

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