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Implementing ultra-high-value floating tunable CMOS resistors

Electronics letters, 2008, Vol.44 (5), p.349

2008

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Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

IEEE journal of solid-state circuits, 2008-07, Vol.43 (7), p.1699-1710

2008

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Real-time interaction between a neuromorphic electronic circuit and the spinal cord

IEEE transactions on neural systems and rehabilitation engineering, 2001-09, Vol.9 (3), p.319-326

2001

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Ultra-low power subthreshold current-mode logic utilising PMOS load device

Electronics letters, 2007, Vol.43 (17), p.911-913

2007

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Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, 2007, p.304-307

2007

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Via-Programmable Structured ASIC Fabric Based on MCML Cells: Design Flow and Implementation

2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006, Vol.1, p.85-88

2006

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Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.-2896

2006

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An improved analytic method to calculate emitter follower delay including emitter resistance

Proceedings of the 39th Midwest Symposium on Circuits and Systems, 1996, Vol.1, p.309-312 vol.1

Brauer, E.J.

1996

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An algorithm for functional verification of digital ECL circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-12, Vol.14 (12), p.1546-1556

1995

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Determining the network parameters of the amphibian vision system

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002, 2002, Vol.1, p.I-412

2002

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Performance evaluation of CMOS low drop-out voltage regulators

The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04, 2004, Vol.1, p.I-141

2004

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Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

2006 IFIP International Conference on Very Large Scale Integration, 2006, p.234-238

2006

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Graphical user interface for functional neuromuscular stimulation system

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), 1999, Vol.2, p.1105-1108 vol. 2

1999

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A VLSI circuit of lamprey unit pattern generator

IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339), 1999, Vol.4, p.2319-2322 vol.4

1999

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Neuromorphic aVLSI circuit of lamprey unit pattern generator

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), 1999, Vol.2, p.1095-1098 vol. 2

1999

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Hardware implementation of a neural network pattern shaper algorithm

IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339), 1999, Vol.4, p.2315-2318 vol.4

1999

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Analog VLSI-spinal cord interface for motor control

Proceedings of the First Joint BMES/EMBS Conference : serving humanity advancing technology, Oct. 13-16, 99, Atlanta, GA, USA, 1999, Vol.1, p.488 vol.1-488

1999

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A full-swing bootstrapped BiCMOS buffer

Proceedings Great Lakes Symposium on VLSI, 1997, p.8-13

1997

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Functional verification of ECL circuits including voltage regulators

1993 IEEE International Symposium on Circuits and Systems (ISCAS), 1993, p.1710-1713 vol.3

1993

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Experimental results of 6 neuron VLSI circuit of lamprey unit pattern generator

Proceedings of the First Joint BMES/EMBS Conference : serving humanity advancing technology, Oct. 13-16, 99, Atlanta, GA, USA, 1999, Vol.1, p.372 vol.1-372

1999

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Sensitivity analysis of an analog circuit model of lamprey unit pattern generator

Proceedings of International Conference on Neural Networks (ICNN'97), 1997, Vol.2, p.975-979 vol.2

1997

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An analytic method to calculate emitter follower delay using trial functions in coupled node equations

1995 IEEE International Symposium on Circuits and Systems (ISCAS), 1995, Vol.3, p.1580-1583 vol.3

1995

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Estimating node voltages in bipolar circuits using linear programming

1995 IEEE International Symposium on Circuits and Systems (ISCAS), 1995, Vol.2, p.901-903 vol.2

1995

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An analytic method for calculating current sharing in emitter-coupled bipolar transistors

Proceedings of 36th Midwest Symposium on Circuits and Systems, 1993, p.887-890 vol.2

1993

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Analog circuit model of lamprey unit pattern generator

Proceedings Great Lakes Symposium on VLSI, 1997, p.137-142

1997

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Implementing ultra-high-value floating tunable CMOS resistors

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Real-time interaction between a neuromorphic electronic circuit and the spinal cord

Ultra-low power subthreshold current-mode logic utilising PMOS load device

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Via-Programmable Structured ASIC Fabric Based on MCML Cells: Design Flow and Implementation

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design

An improved analytic method to calculate emitter follower delay including emitter resistance

An algorithm for functional verification of digital ECL circuits

Determining the network parameters of the amphibian vision system

Performance evaluation of CMOS low drop-out voltage regulators

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

Graphical user interface for functional neuromuscular stimulation system

A VLSI circuit of lamprey unit pattern generator

Neuromorphic aVLSI circuit of lamprey unit pattern generator

Hardware implementation of a neural network pattern shaper algorithm

Analog VLSI-spinal cord interface for motor control

A full-swing bootstrapped BiCMOS buffer

Functional verification of ECL circuits including voltage regulators

Experimental results of 6 neuron VLSI circuit of lamprey unit pattern generator

Sensitivity analysis of an analog circuit model of lamprey unit pattern generator

An analytic method to calculate emitter follower delay using trial functions in coupled node equations

Estimating node voltages in bipolar circuits using linear programming

An analytic method for calculating current sharing in emitter-coupled bipolar transistors

Analog circuit model of lamprey unit pattern generator

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