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High Frequency TDDB of Reinforced Isolation Dielectric Systems

2020 IEEE International Reliability Physics Symposium (IRPS), 2020, p.1-4

2020

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Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

TRANSACTIONS OF THE JAPAN INSTITUTE OF ELECTRONICS PACKAGING, 2012, Vol.5 (1), p.122-131

2012

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High voltage time-dependent dielectric breakdown in stacked intermetal dielectrics

2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.P-GD.9-1-P-GD.9-5

2018

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Effect of intermetallic formation on electromigration reliability of TSV-microbump joints in 3D interconnect

2012 IEEE 62nd Electronic Components and Technology Conference, 2012, p.319-325

2012

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The properties of thermal hillocks as a function of linewidth and process parameter in Al-on-chemical-vapor-deposited W films

Journal of materials research, 1993-05, Vol.8 (5), p.1010-1018

1993

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BEOL variability and impact on RC extraction

Proceedings. 42nd Design Automation Conference, 2005, 2005, p.758-759

2005

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Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology

2012 IEEE 62nd Electronic Components and Technology Conference, 2012, p.1062-1067

2012

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Microstructural characterization of Al 98.5wt. % Si 1.0wt. % Cu 0.5wt. % on chemical-vapor-deposited W

Journal of materials research, 1993-05, Vol.8 (5), p.1001-1009

1993

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Microstructural characterization of Al98.5wt. %Si1.0wt. %Cu0.5wt. % on chemical-vapor-deposited W

Journal of materials research, 1993-05, Vol.8 (5), p.1001-1009

1993

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Hillocks on half-micron aluminum lines

Journal of materials research, 1991-09, Vol.6 (9), p.1817-1819

1991

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BEOL variability and impact on RC extraction

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.758-759

2005

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Benchmarks for interconnect parasitic resistance and capacitance

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings, 2003, p.163-168

2003

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Interconnect modeling for copper/low-k technologies

17th International Conference on VLSI Design. Proceedings, 2004, p.425-427

2004

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Thermal hillocks on half-micron aluminum lines: the next reliability issue?

1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference, 1991, p.256-257

1991

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High Frequency TDDB of Reinforced Isolation Dielectric Systems

Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

High voltage time-dependent dielectric breakdown in stacked intermetal dielectrics

Effect of intermetallic formation on electromigration reliability of TSV-microbump joints in 3D interconnect

The properties of thermal hillocks as a function of linewidth and process parameter in Al-on-chemical-vapor-deposited W films

BEOL variability and impact on RC extraction

Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology

Microstructural characterization of Al 98.5wt. % Si 1.0wt. % Cu 0.5wt. % on chemical-vapor-deposited W

Microstructural characterization of Al98.5wt. %Si1.0wt. %Cu0.5wt. % on chemical-vapor-deposited W

Hillocks on half-micron aluminum lines

BEOL variability and impact on RC extraction

Benchmarks for interconnect parasitic resistance and capacitance

Interconnect modeling for copper/low-k technologies

Thermal hillocks on half-micron aluminum lines: the next reliability issue?

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