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Onset-age of bipolar disorders at six international sites

Journal of affective disorders, 2010-02, Vol.121 (1), p.143-146

2010

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Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects

Journal of electronic testing, 2019-04, Vol.35 (2), p.191-200

2019

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Comparison of psychotic bipolar disorder, schizoaffective disorder, and schizophrenia: an international, multisite study

Acta psychiatrica Scandinavica, 2016-01, Vol.133 (1), p.34-43

2016

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NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time

Journal of electronic testing, 2016-06, Vol.32 (3), p.315-328

2016

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Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations

Microelectronics and reliability, 2016-12, Vol.67, p.150-158

2016

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An On-Chip Sensor to Monitor NBTI Effects in SRAMs

Journal of electronic testing, 2014-04, Vol.30 (2), p.159-169

2014

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A Hybrid Approach for Detection and Correction of Transient Faults in SoCs

IEEE transactions on dependable and secure computing, 2010-10, Vol.7 (4), p.439-445

2010

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Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

Journal of electronic testing, 2020-04, Vol.36 (2), p.271-284

2020

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Review of Manufacturing Process Defects and Their Effects on Memristive Devices

Journal of electronic testing, 2021-08, Vol.37 (4), p.427-437

2021

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Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing?

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2023, p.167-168

Bolzani Poehls, L. M.

2023

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Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs

2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021, p.1-6

2021

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Enabling concurrent clock and power gating in an industrial design flow

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.334-339

2009

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Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016, p.487-492

2016

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Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

2022 IEEE 23rd Latin American Test Symposium (LATS), 2022, p.1-6

2022

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Analysing NBTI Impact on SRAMs with Resistive Defects

Journal of electronic testing, 2017-10, Vol.33 (5), p.637-655

2017

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Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs

2015 28th International Conference on VLSI Design, 2015, p.405-410

2015

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A new hybrid fault detection technique for systems-on-a-chip

IEEE transactions on computers, 2006-02, Vol.55 (2), p.185-198

2006

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A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Microelectronics and reliability, 2018-09, Vol.88-90, p.355-359

2018

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Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach

Journal of electronic testing, 2012-12, Vol.28 (6), p.777-789

2012

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A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Journal of electronic testing, 2024-04, Vol.40 (2), p.245-257

2024

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Evaluating a New RRAM Manufacturing Test Strategy

2023 IEEE 24th Latin American Test Symposium (LATS), 2023, p.1-6

2023

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Analyzing the Use of Temperature to Facilitate Fault Propagation in ReRAMs

2024 IEEE 25th Latin American Test Symposium (LATS), 2024, p.1-6

2024

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On-line detection of control-flow errors in SoCs by means of an infrastructure IP core

2005 International Conference on Dependable Systems and Networks (DSN'05), 2005, p.50-58

2005

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Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

2012 13th Latin American Test Workshop (LATW), 2012, p.1-6

2012

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An integrated approach for increasing the soft-error detection capabilities in SoCs processors

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005, p.445-453

2005

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Onset-age of bipolar disorders at six international sites

Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects

Comparison of psychotic bipolar disorder, schizoaffective disorder, and schizophrenia: an international, multisite study

NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations

An On-Chip Sensor to Monitor NBTI Effects in SRAMs

A Hybrid Approach for Detection and Correction of Transient Faults in SoCs

Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

Review of Manufacturing Process Defects and Their Effects on Memristive Devices

Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing?

Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs

Enabling concurrent clock and power gating in an industrial design flow

Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects

Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

Analysing NBTI Impact on SRAMs with Resistive Defects

Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs

A new hybrid fault detection technique for systems-on-a-chip

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach

A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Evaluating a New RRAM Manufacturing Test Strategy

Analyzing the Use of Temperature to Facilitate Fault Propagation in ReRAMs

On-line detection of control-flow errors in SoCs by means of an infrastructure IP core

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

An integrated approach for increasing the soft-error detection capabilities in SoCs processors

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