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Study of loss in superconducting coplanar waveguide resonators
Journal of applied physics, 2011-03, Vol.109 (6), p.063915-063915-10
2011
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Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits
IEEE transactions on applied superconductivity, 2016-04, Vol.26 (3), p.1-10
2016
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Advanced Fabrication Processes for Superconductor Electronics: Current Status and New Developments
IEEE transactions on applied superconductivity, 2019-08, Vol.29 (5), p.1-13
2019
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Extremely large area (88 mm × 88 mm) superconducting integrated circuit (ELASIC)
Scientific reports, 2023-07, Vol.13 (1), p.11796-11796, Article 11796
2023
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Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al- \hbox\hbox Josephson Junctions for VLSI Circuits
IEEE transactions on applied superconductivity, 2015-06, Vol.25 (3), p.1-12
2015
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Inductance of superconductor integrated circuit features with sizes down to 120 nm
Superconductor science & technology, 2021-07, Vol.34 (8), p.85005
2021
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Development of Self-Shunted Josephson Junctions for a Ten-Superconductor-Layer Fabrication Process: Nb/NbN x /Nb Junctions
IEEE transactions on applied superconductivity, 2024-05, Vol.34 (3), p.1-8
2024
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Broadband squeezed microwaves and amplification with a Josephson travelling-wave parametric amplifier
Nature physics, 2023-05, Vol.19 (5), p.706-713
2023
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Mutual and Self-Inductance in Planarized Multilayered Superconductor Integrated Circuits: Microstrips, Striplines, Bends, Meanders, Ground Plane Perforations
IEEE transactions on applied superconductivity, 2022-08, Vol.32 (5), p.1-31
2022
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Development of Self-Shunted Josephson Junctions for a Ten-Superconductor-Layer Fabrication Process: Nb/NbNx/Nb Junctions
IEEE transactions on applied superconductivity, 2024-05, Vol.34 (3), p.1-8
2024
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Superconductor Electronics Fabrication Process with MoNx Kinetic Inductors and Self-Shunted Josephson Junctions
IEEE transactions on applied superconductivity, 2018-06, Vol.28 (4), p.1-12
2018
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Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in a Planarized Fabrication Process With Nb Ground Planes
IEEE transactions on applied superconductivity, 2023-08, Vol.33 (5), p.1-11
2023
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Progress Toward Superconductor Electronics Fabrication Process With Planarized NbN and NbN/Nb Layers
IEEE transactions on applied superconductivity, 2023-08, Vol.33 (5), p.1-12
2023
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Submicron Nb Microwave Transmission Lines and Components for Single-Flux-Quantum and Analog Large-Scale Superconducting Integrated Circuits
IEEE transactions on applied superconductivity, 2017-06, Vol.27 (4), p.1-5
2017
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Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions
IEEE transactions on applied superconductivity, 2019-08, Vol.29 (5), p.1-8
2019
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Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process With 8 Niobium Layers
IEEE transactions on applied superconductivity, 2015-06, Vol.25 (3), p.1-5
2015
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Fabrication of Magnetic Calorimeter Arrays With Buried Wiring
IEEE transactions on applied superconductivity, 2019-08, Vol.29 (5), p.1-6
2019
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Diagnosis of Factors Impacting Yield in Multilayer Devices for Superconducting Electronics
IEEE transactions on applied superconductivity, 2019-08, Vol.29 (5), p.1-4
2019
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Analysis of Multilayer Devices for Superconducting Electronics by High-Resolution Scanning Transmission Electron Microscopy and Energy Dispersive Spectroscopy
IEEE transactions on applied superconductivity, 2017-06, Vol.27 (4), p.1-4
2017
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Properties of Unshunted and Resistively Shunted Nb/AlOx-Al/Nb Josephson Junctions With Critical Current Densities From 0.1 to 1 mA/μm2
IEEE transactions on applied superconductivity, 2017-06, Vol.27 (4), p.1-15
2017
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Cryogenic Qubit Integration for Quantum Computing
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.504-514
2018
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Large Scale Cryogenic Integration Approach for Superconducting High-Performance Computing
2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.675-683
2017
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Waferscale S-MCM for High Performance Computing
2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, p.582-588
2020
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Developments toward a 250-nm, Fully Planarized Fabrication Process with Ten Superconducting Layers and Self-Shunted Josephson Junctions
2017 16th International Superconductive Electronics Conference (ISEC), 2017, p.1-3
2017
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Interconnect Scheme for Die-to-Die and Die-to-Wafer-Level Heterogeneous Integration for High-Performance Computing
2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, p.1611-1621
2019
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