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Area-efficient linear regulator with ultra-fast load regulation

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.933-940

2005

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Dynamic sleep transistor and body bias for active leakage power control of microprocessors

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1838-1845

2003

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A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.838-845

2005

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Forward body bias for microprocessors in 130-nm technology generation and beyond

IEEE journal of solid-state circuits, 2003-05, Vol.38 (5), p.696-701

2003

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A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1866-1875

2003

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Accurate on-chip interconnect evaluation: a time-domain technique

IEEE journal of solid-state circuits, 1999-05, Vol.34 (5), p.623-631

1999

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5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1421

2002

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1536-1543

2004

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9)

2004

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Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1536-1543

2004

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64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.444-538 Vol.1

2004

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5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1421-1432

2002

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A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551), 2004, Vol.6, p.4702-4707 Vol.6

2004

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17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18/spl mu/m logic CMOS technology

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003, p.149-152

2003

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An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18 /spl mu/m digital CMOS process

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003, p.141-144

2003

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10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 /spl mu/m digital CMOS process

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003, p.181-184

2003

Volltextzugriff (PDF)

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Area-efficient linear regulator with ultra-fast load regulation

Dynamic sleep transistor and body bias for active leakage power control of microprocessors

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

Forward body bias for microprocessors in 130-nm technology generation and beyond

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

Accurate on-chip interconnect evaluation: a time-domain technique

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process

Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process

64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18/spl mu/m logic CMOS technology

An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18 /spl mu/m digital CMOS process

10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 /spl mu/m digital CMOS process

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