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Design of a Master Device for the Multifunction Vehicle Bus

IEEE transactions on vehicular technology, 2007-11, Vol.56 (6), p.3695-3708

2007

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Comparison of two designs for the multifunction vehicle bus

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-05, Vol.25 (5), p.797-805

2006

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Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

Reliability engineering & system safety, 2016-07, Vol.151, p.1-9

2016

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FPGA solution for matrix converter double sided space vector modulation algorithm

International journal of electronics, 2008-11, Vol.95 (11), p.1181-1200

2008

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Matrix Converter Protection and Computational Capabilities Based on a System on Chip Design With an FPGA

IEEE transactions on power electronics, 2011-01, Vol.26 (1), p.272-287

2011

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Hardware implementation of optical flow constraint equation using FPGAs

Computer vision and image understanding, 2005-06, Vol.98 (3), p.462-490

2005

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Reconfigurable microstepping control of stepper motors using FPGA embedded RAM

IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468), 2003, Vol.3, p.2221-2226 Vol.3

2003

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Simulation environment to verify industrial communication circuits

IEEE 2002 28th Annual Conference of the Industrial Electronics Society. IECON 02, 2002, Vol.3, p.2339-2344 vol.3

2002

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A Self-Reconfiguration Framework for Multiprocessor CSoPCs

Field Programmable Logic and Application, 2004, p.1124-1126

2004

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High Throughput Serpent Encryption Implementation

Field Programmable Logic and Application, 2004, p.996-1000

2004

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Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design

Field Programmable Logic and Application, 2004, p.965-969

2004

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Operational amplifiers in discrete time control systems: Influence of the Rail-to-Rail feature on their performance

WSEAS Transactions on Electronics, 2008-02, Vol.5, p.25-34

2008

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Multiprocessor SoPC-Core for FAT volume computation

Microprocessors and microsystems, 2005-12, Vol.29 (10), p.421-434

2005

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DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus

2009 29th IEEE International Conference on Distributed Computing Systems Workshops, 2009, p.472-475

2009

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Review of basic guidelines when designing mixed PCBs for SI and EMI

2008 34th Annual Conference of IEEE Industrial Electronics, 2008, p.338-342

2008

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Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements

Field Programmable Logic and Application, 2003, p.497-506

2003

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Simulink/Modelsim Simulabel VHDL PID Core for Industrial SoPC Multiaxis Controllers

IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics, 2006, p.3007-3011

2006

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OSCRYB: Open Source CRYpto-Bridge for Secure Ethernet point-to-point Industrial Communications

IECON 2007 - 33rd Annual Conference of the IEEE Industrial Electronics Society, 2007, p.2639-2644

2007

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Decompression dual core for SoPC applications in high speed FPGA

IECON 2007 - 33rd Annual Conference of the IEEE Industrial Electronics Society, 2007, p.738-743

2007

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Architecture of a Real-Time Wavelet Transform Calculation SoPC Core for Industrial Applications

IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics, 2006, p.2944-2949

2006

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Run-time reconfigurable hybrid multiprocessor cores

2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04, 2004, Vol.3, p.1345-1350 Vol. 3

2004

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Adaptive image brightness and contrast enhancement circuit for real-time vision systems

Proceedings of IEEE International Conference on Industrial Technology 2000 (IEEE Cat. No.00TH8482), 2000, Vol.1, p.421-426 vol.2

2000

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Robustness Analysis of Different AES Implementations on SRAM Based FPGAs

2011 International Conference on Reconfigurable Computing and FPGAs, 2011, p.255-260

2011

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Overview of FPGA-Based Multiprocessor Systems

2009 International Conference on Reconfigurable Computing and FPGAs, 2009, p.273-278

2009

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Known-blocking. Synchronization method for reliable processor using TMR & DPR in SRAM FPGAs

2011 VII Southern Conference on Programmable Logic (SPL), 2011, p.57-62

2011

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Design of a Master Device for the Multifunction Vehicle Bus

Comparison of two designs for the multifunction vehicle bus

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

FPGA solution for matrix converter double sided space vector modulation algorithm

Matrix Converter Protection and Computational Capabilities Based on a System on Chip Design With an FPGA

Hardware implementation of optical flow constraint equation using FPGAs

Reconfigurable microstepping control of stepper motors using FPGA embedded RAM

Simulation environment to verify industrial communication circuits

A Self-Reconfiguration Framework for Multiprocessor CSoPCs

High Throughput Serpent Encryption Implementation

Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design

Operational amplifiers in discrete time control systems: Influence of the Rail-to-Rail feature on their performance

Multiprocessor SoPC-Core for FAT volume computation

DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus

Review of basic guidelines when designing mixed PCBs for SI and EMI

Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements

Simulink/Modelsim Simulabel VHDL PID Core for Industrial SoPC Multiaxis Controllers

OSCRYB: Open Source CRYpto-Bridge for Secure Ethernet point-to-point Industrial Communications

Decompression dual core for SoPC applications in high speed FPGA

Architecture of a Real-Time Wavelet Transform Calculation SoPC Core for Industrial Applications

Run-time reconfigurable hybrid multiprocessor cores

Adaptive image brightness and contrast enhancement circuit for real-time vision systems

Robustness Analysis of Different AES Implementations on SRAM Based FPGAs

Overview of FPGA-Based Multiprocessor Systems

Known-blocking. Synchronization method for reliable processor using TMR & DPR in SRAM FPGAs

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