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Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems

Journal of signal processing systems, 2017-06, Vol.87 (3), p.271-286

2017

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ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

International Journal of Reconfigurable Computing, 2019-11, Vol.2019, p.1-19

2019

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Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application

International journal of circuit theory and applications, 2017-12, Vol.45 (12), p.2243-2259

2017

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FPGA-Centric Design Process for Avionic Simulation and Test

IEEE transactions on aerospace and electronic systems, 2018-06, Vol.54 (3), p.1047-1065

2018

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An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules

International journal of circuit theory and applications, 2020-08, Vol.48 (8), p.1274-1290

2020

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Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks

Journal of electronic imaging, 2019-05, Vol.28 (3), p.1

2019

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Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays

Journal of intelligent manufacturing, 2018-03, Vol.29 (3), p.629-640

2018

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A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis

Computación y Sistemas, 2019-01, Vol.23 (1), p.213-230

2019

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A Model-Driven Design Framework for Massively Parallel Embedded Systems

ACM transactions on embedded computing systems, 2011-11, Vol.10 (4), p.1-36

2011

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An Embedded Multi-Sensor Data Fusion Design for Vehicle Perception Tasks

Journal of communications, 2018, Vol.13 (1), p.8-14

2018

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Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation

Applied Reconfigurable Computing, p.168-176

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Combining Artificial Intelligence and Edge Computing to Reshape Distance Education (Case Study: K-12 Learners)

Artificial Intelligence in Education, p.218-230

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An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Elektrik : Turkish journal of electrical engineering & computer sciences, 2020-01, Vol.28 (3), p.1656-1672

2020

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A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design

EURASIP journal on embedded systems, 2011-03, Vol.2011 (1), p.569031-569031

2011

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An efficient design methodology for hybrid avionic test systems

2010 IEEE 15th Conference on Emerging Technologies & Factory Automation (ETFA 2010), 2010, p.1-4

2010

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Multi-Sensor Fusion for Obstacle Detection and Recognition: A Belief-Based Approach

2018 21st International Conference on Information Fusion (FUSION), 2018, p.1217-1224

2018

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Multi-level energy/power-aware design methodology for MPSoC

Journal of parallel and distributed computing, 2017-02, Vol.100, p.203-215

2017

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Approximation Algorithm for 3-Dimensional Vehicle Routing Problem for Fleet of Multi-Agents

2018 6th International Conference on Control Engineering & Information Technology (CEIT), 2018, p.1-6

2018

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PETS: Power and energy estimation tool at system-level

Fifteenth International Symposium on Quality Electronic Design, 2014, p.535-542

2014

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AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC), 2016, p.1-7

2016

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An Optimized Software Radio Application Using a Dynamic Slack Reclamation Technique on a Real Platform OMAP 3530

2017 IEEE/ACS 14th International Conference on Computer Systems and Applications (AICCSA), 2017, p.637-644

2017

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New MIP model for multiprocessor scheduling problem with communication delays

Optimization letters, 2017-08, Vol.11 (6), p.1091-1107

2017

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Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, 2015, p.165-165

2015

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An Efficient Hardware Implementation of TimSort and MergeSort Algorithms Using High Level Synthesis

2017 International Conference on High Performance Computing & Simulation (HPCS), 2017, p.580-587

2017

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Communication-centric design for FMC based I/O system

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014, p.1-8

2014

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Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application

FPGA-Centric Design Process for Avionic Simulation and Test

An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules

Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks

Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays

A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis

A Model-Driven Design Framework for Massively Parallel Embedded Systems

An Embedded Multi-Sensor Data Fusion Design for Vehicle Perception Tasks

Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation

Combining Artificial Intelligence and Edge Computing to Reshape Distance Education (Case Study: K-12 Learners)

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design

An efficient design methodology for hybrid avionic test systems

Multi-Sensor Fusion for Obstacle Detection and Recognition: A Belief-Based Approach

Multi-level energy/power-aware design methodology for MPSoC

Approximation Algorithm for 3-Dimensional Vehicle Routing Problem for Fleet of Multi-Agents

PETS: Power and energy estimation tool at system-level

AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture

An Optimized Software Radio Application Using a Dynamic Slack Reclamation Technique on a Real Platform OMAP 3530

New MIP model for multiprocessor scheduling problem with communication delays

Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System

An Efficient Hardware Implementation of TimSort and MergeSort Algorithms Using High Level Synthesis

Communication-centric design for FMC based I/O system

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