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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.197-209

2019

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A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.204-206

2018

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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.107-118

2011

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An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.121-131, Article 121

2008

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A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

2011 IEEE International Solid-State Circuits Conference, 2011, p.498-500

2011

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A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.278-613

2008

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A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.434-435

2010

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An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.492-617

2007

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A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

2010 Symposium on VLSI Circuits, 2010, p.193-194

2010

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Implementation of a Ball and Plate Control System Using Sliding Mode Control

IEEE access, 2018-01, Vol.6, p.32401-32408

2018

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Embedded Model Predictive Control for Enhancing Tracking Performance of a Ball-and-Plate System

IEEE access, 2019, Vol.7, p.39652-39659

2019

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A Study on the Implementation of a Ball and Plate System using LW-RCP and Machine Vision based on Odroid

Journal of Institute of Control, Robotics and Systems, 2020-04, Vol.26 (4), p.213-221

2020

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Administering Pesticide Assays in In Vivo-Implanted Biosensors

Australian journal of chemistry, 2008-01, Vol.61 (10), p.826

2008

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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

Implementation of a Ball and Plate Control System Using Sliding Mode Control

Embedded Model Predictive Control for Enhancing Tracking Performance of a Ball-and-Plate System

A Study on the Implementation of a Ball and Plate System using LW-RCP and Machine Vision based on Odroid

Administering Pesticide Assays in In Vivo-Implanted Biosensors

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