UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 1.285

Sortiert nach

Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits

Journal of micromechanics and microengineering, 2017-02, Vol.27 (2), p.25011

2017

Link zum Volltext

Verfügbarkeit prüfen

Independent interlayer microfluidic cooling for heterogeneous 3D IC applications

Electronics letters, 2013-03, Vol.49 (6), p.404-406

2013

Link zum Volltext

Verfügbarkeit prüfen

Interfacial Effects During Thermal Cycling of Cu-Filled Through-Silicon Vias (TSV)

Journal of electronic materials, 2012-02, Vol.41 (2), p.322-335

2012

Link zum Volltext

Verfügbarkeit prüfen

Interface-related reliability challenges in 3-D interconnect systems with through-silicon vias

JOM (1989), 2011-10, Vol.63 (10), p.70-77

2011

Link zum Volltext

Verfügbarkeit prüfen

Optical transmission of polymer pillars for chip I/O optical interconnections

IEEE photonics technology letters, 2004-01, Vol.16 (1), p.117-119

2004

Link zum Volltext
IEEE_Xplore

Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink

IEEE electron device letters, 2006-02, Vol.27 (2), p.117-119

2006

Link zum Volltext
IEEE_Xplore

Sea-of-leads MEMS I/O interconnects for low-k IC packaging

Journal of microelectromechanical systems, 2006-06, Vol.15 (3), p.523-530

2006

Link zum Volltext
IEEE_Xplore

Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

IEEE transactions on electron devices, 2004-07, Vol.51 (7), p.1069-1077

2004

Link zum Volltext
IEEE_Xplore

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

IEEE transactions on electron devices, 2003-10, Vol.50 (10), p.2039-2048

2003

Link zum Volltext
IEEE_Xplore

Electrical and Optical Chip I/O Interconnections for Gigascale Systems

IEEE transactions on electron devices, 2007-09, Vol.54 (9), p.2426-2437

2007

Link zum Volltext
IEEE_Xplore

Flexible pillars for displacement compensation in optical chip assembly

IEEE photonics technology letters, 2006-04, Vol.18 (8), p.974-976

2006

Link zum Volltext
IEEE_Xplore

Chip-level waveguide-mirror-pillar optical interconnect structure

IEEE photonics technology letters, 2006-08, Vol.18 (15), p.1672-1674

2006

Link zum Volltext
IEEE_Xplore

Independent interlayer microfluidic cooling for heterogeneous 3D IC applications

Electronics letters, 2013-03, Vol.49 (6), p.1-1

2013

Link zum Volltext

Verfügbarkeit prüfen

Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections

IEEE photonics technology letters, 2003-11, Vol.15 (11), p.1567-1569

2003

Link zum Volltext
IEEE_Xplore

Thermomechanical strain measurements by synchrotron x-ray diffraction and data interpretation for through-silicon vias

Applied physics letters, 2013-07, Vol.103 (2)

2013

Link zum Volltext

Verfügbarkeit prüfen

Self-aligning silicon interposer tiles and silicon bridges for large nanophotonics enabled systems

Electronics letters, 2014-09, Vol.50 (20), p.1-1

2014

Link zum Volltext

Verfügbarkeit prüfen

Self-aligning silicon interposer tiles and silicon bridges for large nanophotonics enabled systems

Electronics letters, 2014-09, Vol.50 (20), p.1475-1477

2014

Link zum Volltext

Verfügbarkeit prüfen

Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors

IEEE transactions on electron devices, 2004-07, Vol.51 (7), p.1084-1090

2004

Link zum Volltext
IEEE_Xplore

Design, Fabrication, and Characterization of Freestanding Mechanically Flexible Interconnects Using Curved Sacrificial Layer

IEEE transactions on components, packaging, and manufacturing technology (2011), 2012-04, Vol.2 (4), p.561-568

2012

Link zum Volltext
IEEE_Xplore

Sea of leads: a disruptive paradigm for a system-on-a-chip (SoC)

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001, p.280-281

2001

Link zum Volltext
IEEE_Xplore

Chip-to-Module Interconnections Using “Sea of Leads” Technology

MRS bulletin, 2003-01, Vol.28 (1), p.61-67

2003

Link zum Volltext

Verfügbarkeit prüfen

Trigeminal Schwannomas in Neurofibromatosis 2

Journal of Neurological Surgery Part B: Skull Base, 2012, Vol.73 (S 02)

2012

Link zum Volltext

Verfügbarkeit prüfen

The effects of a low-dose intravenous insulin infusion upon plasma glucose and non-esterified fatty acid levels in very obese and non-obese human subjects

Diabetologia, 1981-06, Vol.20 (6), p.592-596

1981

Link zum Volltext

Verfügbarkeit prüfen

Two-phase flow and heat transfer in pin-fin enhanced micro-gaps

13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2012, p.1084-1089

2012

Link zum Volltext
IEEE_Xplore

Electrical test strategies for a wafer-level packaging technology

IEEE transactions on electronics packaging manufacturing, 2003-10, Vol.26 (4), p.267-272

2003

Link zum Volltext
IEEE_Xplore

1 – 25 von 1.285

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(934)
Mit Volltextzugriff
(1.095)

Publikationsform

4 weitere anzeigen...

Weniger anzeigen...

Sprache

Englisch
(1.045)
Französisch
(229)
Japanisch
(59)
Türkisch
(9)
Deutsch
(5)
Russisch
(3)
Arabisch
(2)
Spanisch
(1)

3 weitere anzeigen...

Weniger anzeigen...

Erscheinungsjahr

n.n

Thema

Science & Technology
(644)
Life Sciences & Biomedicine
(386)
Humans
(329)
Male
(216)
Female
(209)
Technology
(173)
Physical Sciences
(169)
Adult
(141)
Biological And Medical Sciences
(135)
Medical Sciences
(115)
Engineering
(112)
Middle Aged
(109)
Chemistry
(83)
Aged
(77)
Physics
(76)
Exact Sciences And Technology
(75)
Surgery
(71)
Engineering, Electrical & Electronic
(70)
Child
(66)
Adolescent
(65)

15 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

... seit 30 Tagen
(2)
... seit 90 Tagen
(12)

Menü

Weitere Dienste

Einstellungen

Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits

Independent interlayer microfluidic cooling for heterogeneous 3D IC applications

Interfacial Effects During Thermal Cycling of Cu-Filled Through-Silicon Vias (TSV)

Interface-related reliability challenges in 3-D interconnect systems with through-silicon vias

Optical transmission of polymer pillars for chip I/O optical interconnections

Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink

Sea-of-leads MEMS I/O interconnects for low-k IC packaging

Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

Electrical and Optical Chip I/O Interconnections for Gigascale Systems

Flexible pillars for displacement compensation in optical chip assembly

Chip-level waveguide-mirror-pillar optical interconnect structure

Independent interlayer microfluidic cooling for heterogeneous 3D IC applications

Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections

Thermomechanical strain measurements by synchrotron x-ray diffraction and data interpretation for through-silicon vias

Self-aligning silicon interposer tiles and silicon bridges for large nanophotonics enabled systems

Self-aligning silicon interposer tiles and silicon bridges for large nanophotonics enabled systems

Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors

Design, Fabrication, and Characterization of Freestanding Mechanically Flexible Interconnects Using Curved Sacrificial Layer

Sea of leads: a disruptive paradigm for a system-on-a-chip (SoC)

Chip-to-Module Interconnections Using “Sea of Leads” Technology

Trigeminal Schwannomas in Neurofibromatosis 2

The effects of a low-dose intravenous insulin infusion upon plasma glucose and non-esterified fatty acid levels in very obese and non-obese human subjects

Two-phase flow and heat transfer in pin-fin enhanced micro-gaps

Electrical test strategies for a wafer-level packaging technology

Suchergebnisse filtern