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Novel High-Speed Ternary Logic using Step-shaped Threshold Switch

IEEE electron device letters, 2023-03, Vol.44 (3), p.1-1

2023

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Bidirectional Precharge and Negative Bias Scheme for Program Disturbance Suppression in 3-D NAND Flash Memory

IEEE transactions on electron devices, 2023-12, Vol.70 (12), p.6313-6317

2023

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Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors

IEEE transactions on electron devices, 2023-12, Vol.70 (12), p.6151-6156

2023

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Investigation of Electrothermal Characteristics in Silicon Forksheet FETs for Sub-3-nm Node

IEEE transactions on electron devices, 2023-12, Vol.70 (12), p.6132-6137

2023

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Sensitivity of Source/Drain Critical Dimension Variations for Sub-5-nm Node Fin and Nanosheet FETs

IEEE transactions on electron devices, 2020-01, Vol.67 (1), p.258-262

2020

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Optimization of Process Parameters on Short-Term Retention for Charge-Trapping 3-D NAND Flash Memories Using Novel Neural Networks Approach

IEEE transactions on electron devices, 2023-08, Vol.70 (8), p.4157-4162

2023

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Enhancement of ISPP Efficiency Using Neural Network-Based Optimization of 3-D NAND Cell

IEEE transactions on electron devices, 2023-07, Vol.70 (7), p.3504-3510

2023

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Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme

IEEE transactions on electron devices, 2020-07, Vol.67 (7), p.2732-2737

2020

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TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning Scheme

IEEE transactions on electron devices, 2021-03, Vol.68 (3), p.1031-1036

2021

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Metal Source-/Drain-Induced Performance Boosting of Sub-7-nm Node Nanosheet FETs

IEEE transactions on electron devices, 2019-04, Vol.66 (4), p.1868-1873

2019

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Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail

IEEE transactions on electron devices, 2022-03, Vol.69 (3), p.894-899

2022

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Study on Random Dopant Fluctuation in Core-Shell Tunneling Field-Effect Transistors

IEEE transactions on electron devices, 2018-08, Vol.65 (8), p.3131-3135

2018

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Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics

IEEE transactions on electron devices, 2016-09, Vol.63 (9), p.3399-3405

2016

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Improved Long-Term Responses of Au-Decorated Si Nanowire FET Sensor for NH3 Detection

IEEE sensors journal, 2020-03, Vol.20 (5), p.2270-2277

2020

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Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

IEEE access, 2020, Vol.8, p.189395-189403

2020

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Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs

IEEE journal of the Electron Devices Society, 2018-01, Vol.6, p.942-947

2018

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A Review of Multi-Modal Learning from the Text-Guided Visual Processing Viewpoint

Sensors (Basel, Switzerland), 2022-09, Vol.22 (18), p.6816

2022

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Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

IEEE access, 2020, Vol.8, p.35873-35881

2020

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Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications

Japanese Journal of Applied Physics, 2019-04, Vol.58 (SB), p.SBBA12

2019

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Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

IEEE access, 2021, Vol.9, p.29071-29077

2021

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Electrical characteristics of 20-nm junctionless Si nanowire transistors

Solid-state electronics, 2012-07, Vol.73, p.7-10

2012

Volltextzugriff (PDF)

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Advanced intelligent systems, 2024-04, Vol.6 (4), p.n/a

2024

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Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node

IEEE access, 2019, Vol.7, p.75762-75767

2019

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Electron trapping and extraction kinetics on carrier diffusion in metal halide perovskite thin films

Journal of materials chemistry. A, Materials for energy and sustainability, 2019, Vol.7 (45), p.25838-25844

2019

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Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain

IEEE access, 2019, Vol.7, p.38593-38596

2019

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Novel High-Speed Ternary Logic using Step-shaped Threshold Switch

Bidirectional Precharge and Negative Bias Scheme for Program Disturbance Suppression in 3-D NAND Flash Memory

Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors

Investigation of Electrothermal Characteristics in Silicon Forksheet FETs for Sub-3-nm Node

Sensitivity of Source/Drain Critical Dimension Variations for Sub-5-nm Node Fin and Nanosheet FETs

Optimization of Process Parameters on Short-Term Retention for Charge-Trapping 3-D NAND Flash Memories Using Novel Neural Networks Approach

Enhancement of ISPP Efficiency Using Neural Network-Based Optimization of 3-D NAND Cell

Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme

TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning Scheme

Metal Source-/Drain-Induced Performance Boosting of Sub-7-nm Node Nanosheet FETs

Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail

Study on Random Dopant Fluctuation in Core-Shell Tunneling Field-Effect Transistors

Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics

Improved Long-Term Responses of Au-Decorated Si Nanowire FET Sensor for NH3 Detection

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs

A Review of Multi-Modal Learning from the Text-Guided Visual Processing Viewpoint

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

Electrical characteristics of 20-nm junctionless Si nanowire transistors

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node

Electron trapping and extraction kinetics on carrier diffusion in metal halide perovskite thin films

Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain

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