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System-Level Simulation of Hardware Spiking Neural Network Based on Synaptic Transistors and I&F Neuron Circuits

IEEE electron device letters, 2018-09, Vol.39 (9), p.1441-1444

2018

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Neurons With Captive Synaptic Devices for Temperature Robust Spiking Neural Networks

IEEE electron device letters, 2024-03, Vol.45 (3), p.492-495

2024

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Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

Journal of applied physics, 2018-10, Vol.124 (15)

2018

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Polysilicon-Channel Synaptic Transistors for Implementation of Short- and Long-Term Memory Characteristics

Biomimetics (Basel, Switzerland), 2023-08, Vol.8 (4), p.368

2023

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A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback FET Co-Integrated With CMOS

IEEE journal of the Electron Devices Society, 2019, Vol.7, p.1080-1084

2019

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A Novel Vector-matrix Multiplication (VMM) Architecture based on NAND Memory Array

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2020, 20(3), 93, pp.242-248

2020

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Grain boundary induced short-term memory effect in fully depleted thin-polysilicon devices

Japanese Journal of Applied Physics, 2019-10, Vol.58 (10), p.101004

2019

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Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

IEEE transactions on electron devices, 2016-03, Vol.63 (3), p.1041-1046

2016

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Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

IEEE access, 2021, Vol.9, p.127841-127851

2021

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Design and Characterization of Semi-Floating-Gate Synaptic Transistor

Micromachines (Basel), 2019-01, Vol.10 (1), p.32

2019

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CMOS Analog Integrate-and-fire Neuron Circuit for Driving Memristor based on RRAM

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(2), 74, pp.174-179

2017

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Input-modulating adaptive neuron circuit employing asymmetric floating-gate MOSFET with two independent control gates

Solid-state electronics, 2020-01, Vol.163, p.107667, Article 107667

2020

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Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(2), 74, pp.210-215

2017

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Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(2), 74, pp.260-264

2017

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Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si structure

Japanese Journal of Applied Physics, 2020-06, Vol.59 (6)

2020

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Hole Trapping Phenomenon at the Grain Boundary of Thin Poly-Si Floating-Body MOSFET and Its Capacitor-Less DRAM Application

Journal of nanoscience and nanotechnology, 2017-05, Vol.17 (5), p.2986-2990

2017

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The Lowering of the Schottky Barrier Height Using an Ultrathin Interlayer to Reduce the Contact Resistance

Journal of nanoscience and nanotechnology, 2016-10, Vol.16 (10), p.10260-10263

2016

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Investigation of transient current characteristics with scaling-down poly-Si body thickness and grain size of 3D NAND flash memory

Solid-state electronics, 2019-02, Vol.152, p.41-45

2019

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Comparison of writing methods of single memory cell with volatile and nonvolatile memory functions

Applied physics express, 2017-06, Vol.10 (6), p.64201

2017

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Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

IEEE electron device letters, 2016-07, Vol.37 (7), p.866-869

2016

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Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

IEEE electron device letters, 2015-12, Vol.36 (12), p.1318-1320

2015

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Gated-thyristor DRAM cell with pillar channel structure

2017 Silicon Nanoelectronics Workshop (SNW), 2017, p.71-72

2017

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An Analysis of Hole Trapping at Grain Boundary or Poly-Si Floating-Body MOSFET

Journal of nanoscience and nanotechnology, 2018-09, Vol.18 (9), p.6584-6587

2018

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Polysilicon-Based Synaptic Transistor and Array Structure for Short/Long-Term Memory

Journal of nanoscience and nanotechnology, 2019-10, Vol.19 (10), p.6066-6069

2019

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Simulation Program with Integrated Circuit Emphasis Compact Modeling of a Dual-Gate Positive-Feedback Field-Effect Transistor for Circuit Simulations

Journal of nanoscience and nanotechnology, 2019-10, Vol.19 (10), p.6417-6421

2019

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System-Level Simulation of Hardware Spiking Neural Network Based on Synaptic Transistors and I&F Neuron Circuits

Neurons With Captive Synaptic Devices for Temperature Robust Spiking Neural Networks

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

Polysilicon-Channel Synaptic Transistors for Implementation of Short- and Long-Term Memory Characteristics

A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback FET Co-Integrated With CMOS

A Novel Vector-matrix Multiplication (VMM) Architecture based on NAND Memory Array

Grain boundary induced short-term memory effect in fully depleted thin-polysilicon devices

Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

Design and Characterization of Semi-Floating-Gate Synaptic Transistor

CMOS Analog Integrate-and-fire Neuron Circuit for Driving Memristor based on RRAM

Input-modulating adaptive neuron circuit employing asymmetric floating-gate MOSFET with two independent control gates

Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors

Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si structure

Hole Trapping Phenomenon at the Grain Boundary of Thin Poly-Si Floating-Body MOSFET and Its Capacitor-Less DRAM Application

The Lowering of the Schottky Barrier Height Using an Ultrathin Interlayer to Reduce the Contact Resistance

Investigation of transient current characteristics with scaling-down poly-Si body thickness and grain size of 3D NAND flash memory

Comparison of writing methods of single memory cell with volatile and nonvolatile memory functions

Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

Gated-thyristor DRAM cell with pillar channel structure

An Analysis of Hole Trapping at Grain Boundary or Poly-Si Floating-Body MOSFET

Polysilicon-Based Synaptic Transistor and Array Structure for Short/Long-Term Memory

Simulation Program with Integrated Circuit Emphasis Compact Modeling of a Dual-Gate Positive-Feedback Field-Effect Transistor for Circuit Simulations

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