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Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

IEEE transactions on circuits and systems. I, Regular papers, 2008-07, Vol.55 (6), p.1485-1494

Baeg, S.

2008

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IEEE_Xplore

A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

IEEE transactions on nuclear science, 2017-06, Vol.64 (6), p.1554-1561

2017

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IEEE_Xplore

An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology

IEEE transactions on nuclear science, 2016-12, Vol.63 (6), p.3003-3009

2016

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IEEE_Xplore

Surface modification for hydrophilic property of stainless steel treated by atmospheric-pressure plasma jet

Surface & coatings technology, 2003-07, Vol.171 (1-3), p.312-316

2003

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Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs

IEEE transactions on nuclear science, 2017-01, Vol.64 (1), p.367-373

2017

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IEEE_Xplore

Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

IEEE transactions on nuclear science, 2016-02, Vol.63 (1), p.385-391

2016

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IEEE_Xplore

Single Event Resilient Dynamic Logic Designs

Journal of electronic testing, 2014-12, Vol.30 (6), p.751-761

2014

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Adi/dt Compensation Technique in Delay Testing by Disconnecting Power Pins

IEEE transactions on instrumentation and measurement, 2009-10, Vol.58 (10), p.3450-3456

Baeg, S

2009

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Radiation reliability benefit of area-optimized interleaved flip-flop layout in 28 nm technology

Microelectronics and reliability, 2019-09, Vol.100-101, p.113440, Article 113440

2019

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An SEU-Tolerant DICE Latch Design With Feedback Transistors

IEEE transactions on nuclear science, 2015-04, Vol.62 (2), p.548-554

2015

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IEEE_Xplore

Null Detector Circuit Design Scheme for Detecting Defective AC-Coupled Capacitors in Differential Signaling

IEEE transactions on instrumentation and measurement, 2009-08, Vol.58 (8), p.2544-2556

Sanghyeon Baeg, Sanghyeon Baeg

2009

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IEEE_Xplore

Toward next-generation primate neuroscience: A collaboration-based strategic plan for integrative neuroimaging

Neuron, 2022-01, Vol.110 (1), p.16-20

2022

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Texture based classification of mass abnormalities in mammograms

Proceedings 13th IEEE Symposium on Computer-Based Medical Systems. CBMS 2000, 2000, p.163-168

2000

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IEEE_Xplore

Efficient Interconnect Test Patterns for Crosstalk and Static Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-11, Vol.25 (11), p.2605-2608

2006

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IEEE_Xplore

Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis

IEEE transactions on very large scale integration (VLSI) systems, 2005-03, Vol.13 (3), p.370-383

2005

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IEEE_Xplore

AC-DC factor sensitivity for DRAM components lifetime under hot-carrier injection

2011 International Reliability Physics Symposium, 2011, p.2D.1.1-2D.1.4

2011

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IEEE_Xplore

Segmentation of mammograms into distinct morphological texture regions

Proceedings. 11th IEEE Symposium on Computer-Based Medical Systems (Cat. No.98CB36237), 1998, p.20-25

1998

Link zum Volltext
IEEE_Xplore

Characterization of WC–CrAlN heterostructures obtained using a cathodic arc ion plating process

Surface & coatings technology, 2003-09, Vol.174, p.303-309

2003

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Transmission Relay Method for Balanced Energy Depletion in Wireless Sensor Networks Using Fuzzy Logic

Fuzzy Systems and Knowledge Discovery, 2005, p.998-1007

2005

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A cost-effective design for testability: clock line control and test generation using selective clocking

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-06, Vol.18 (6), p.850-861

1999

Link zum Volltext
IEEE_Xplore

Structure and properties of WC–CrAlN superlattice films by cathodic arc ion plating process

Thin solid films, 2002-12, Vol.420, p.414-420

2002

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BPPT - Bulk potential protection technique for hardened sequentials

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, p.28-32

2017

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IEEE_Xplore

A study on formation of Al and Al2O3 on the porous paper by DC magnetron sputtering

Surface & coatings technology, 2003-07, Vol.171 (1-3), p.65-70

2003

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Removing JTAG bottlenecks in system interconnect test

2004 International Conferce on Test, 2004, p.173-180

2004

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IEEE_Xplore

AC-JTAG: empowering JTAG beyond testing DC nets

Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001, p.30-37

2001

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IEEE_Xplore

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Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology

Surface modification for hydrophilic property of stainless steel treated by atmospheric-pressure plasma jet

Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs

Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

Single Event Resilient Dynamic Logic Designs

Adi/dt Compensation Technique in Delay Testing by Disconnecting Power Pins

Radiation reliability benefit of area-optimized interleaved flip-flop layout in 28 nm technology

An SEU-Tolerant DICE Latch Design With Feedback Transistors

Null Detector Circuit Design Scheme for Detecting Defective AC-Coupled Capacitors in Differential Signaling

Toward next-generation primate neuroscience: A collaboration-based strategic plan for integrative neuroimaging

Texture based classification of mass abnormalities in mammograms

Efficient Interconnect Test Patterns for Crosstalk and Static Faults

Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis

AC-DC factor sensitivity for DRAM components lifetime under hot-carrier injection

Segmentation of mammograms into distinct morphological texture regions

Characterization of WC–CrAlN heterostructures obtained using a cathodic arc ion plating process

Transmission Relay Method for Balanced Energy Depletion in Wireless Sensor Networks Using Fuzzy Logic

A cost-effective design for testability: clock line control and test generation using selective clocking

Structure and properties of WC–CrAlN superlattice films by cathodic arc ion plating process

BPPT - Bulk potential protection technique for hardened sequentials

A study on formation of Al and Al2O3 on the porous paper by DC magnetron sputtering

Removing JTAG bottlenecks in system interconnect test

AC-JTAG: empowering JTAG beyond testing DC nets

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