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A universal technique for fast and flexible instruction-set architecture simulation

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), 2002, p.22-27

2002

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A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-11, Vol.20 (11), p.1338-1354

2001

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A universal technique for fast and flexible instruction-set architecture simulation

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-12, Vol.23 (12), p.1625-1639

2004

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A universal technique for fast and flexible instruction-set architecture simulation

Proceedings - ACM IEEE Design Automation Conference, 2002, p.22-27

2002

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Querdenken — Voraussetzung für Nachhaltige Entwicklung

Nachhaltige Entwicklung — Strategie für das 21. Jahrhundert?, p.41-55

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Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

Computer Systems: Architectures, Modeling, and Simulation, 2004, p.463-473

2004

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A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.1256-1261 Vol.2

2004

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Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models

Lecture notes in computer science, 2003, p.167-181

2003

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A survey on modeling issues using the machine description language LISA

2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), 2001, Vol.2, p.1137-1140 vol.2

2001

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A methodology and tool suite for C compiler generation from ADL processor models

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.1276-1281 Vol.2

2004

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C Compiler Retargeting Based on Instruction Semantics Models

Design, Automation and Test in Europe, 2005, p.1150-1155

2005

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RTL processor synthesis for architecture exploration and implementation

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.3, p.156-160 Vol.3

2004

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A novel approach for flexible and consistent ADL-driven ASIP design

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.717-722

2004

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Generating production quality software development tools using a machine description language

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001, p.674-678

2001

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Processor/memory co-exploration on multiple abstraction levels

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.966-971

2003

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Instruction encoding synthesis for architecture exploration using hierarchical processor models

Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003, 2003, p.262-267

2003

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Processor/Memory Co-Exploration on Multiple Abstraction Levels

Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003, 2003, p.10966-10966

2003

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A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2001, p.625-630

2001

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Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

Journal of VLSI signal processing, 2006-06, Vol.43 (2-3), p.235-246

2006

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Architecture Implementation Using the Machine Description Language LISA

Proceedings of the 2002 Asia and South Pacific Design Automation Conference, 2002, p.239-239

2002

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RTL Processor Synthesis for Architecture Exploration and Implementation

Proceedings of the conference on Design, automation and test in Europe - Volume 3, 2004, p.30156-30156

2004

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A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms

Proceedings of the conference on Design, automation and test in Europe - Volume 2, 2004, p.21256-21256

2004

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A novel approach for flexible and consisten ADL-driven ASIP design

2004

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Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

International Symposium on System Synthesis (IEEE Cat. No.01EX526), 2001, p.57-62

2001

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A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, 2001, p.625-630

2001

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A universal technique for fast and flexible instruction-set architecture simulation

A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language

A universal technique for fast and flexible instruction-set architecture simulation

A universal technique for fast and flexible instruction-set architecture simulation

Querdenken — Voraussetzung für Nachhaltige Entwicklung

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms

Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models

A survey on modeling issues using the machine description language LISA

A methodology and tool suite for C compiler generation from ADL processor models

C Compiler Retargeting Based on Instruction Semantics Models

RTL processor synthesis for architecture exploration and implementation

A novel approach for flexible and consistent ADL-driven ASIP design

Generating production quality software development tools using a machine description language

Processor/memory co-exploration on multiple abstraction levels

Instruction encoding synthesis for architecture exploration using hierarchical processor models

Processor/Memory Co-Exploration on Multiple Abstraction Levels

A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

Architecture Implementation Using the Machine Description Language LISA

RTL Processor Synthesis for Architecture Exploration and Implementation

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms

A novel approach for flexible and consisten ADL-driven ASIP design

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA

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