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Toward 224-Gb/s Electrical Signaling-Modulation, Equalization, and Channel Options

IEEE transactions on components, packaging, and manufacturing technology (2011), 2021-03, Vol.11 (3), p.451-461

2021

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Noise and Jitter Characterization of High-Speed Interfaces in Heterogeneous Integrated Systems

IEEE transactions on components, packaging, and manufacturing technology (2011), 2021-01, Vol.11 (1), p.109-117

2021

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Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-01, Vol.26 (1), p.166-176

Beyene, W.T.

2007

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A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

IEEE journal of solid-state circuits, 2009-04, Vol.44 (4), p.1235-1247

2009

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A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver

IEEE journal of solid-state circuits, 2013-03, Vol.48 (3), p.636-648

2013

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A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.911-925

2012

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Optimal Terminations for Crosstalk Mitigation of High-Speed Interconnects With Discontinuities Using Modal Signaling

IEEE transactions on components, packaging, and manufacturing technology (2011), 2012-05, Vol.2 (5), p.860-867

2012

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Performance analysis and model-to-hardware correlation of multigigahertz parallel bus with transmit pre-emphasis equalization

IEEE transactions on microwave theory and techniques, 2005-11, Vol.53 (11), p.3568-3577

2005

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Properties of mixed-mode parameters of cascaded balanced networks and their applications in modeling of differential interconnects

IEEE transactions on microwave theory and techniques, 2006-01, Vol.54 (1), p.360-372

2006

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Low-Order Rational Approximation of Interconnects Using Neural-Network Based Pole-Clustering Techniques

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.1501-1504

Beyene, Wendemagegnehu T.

2007

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Return loss characterization and analysis of high-speed serial interface

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS), 2015, p.203-206

2015

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The design of higher-order reference voltage generation circuits for single-ended memory interfaces

2012 IEEE 62nd Electronic Components and Technology Conference, 2012, p.127-132

Beyene, W. T.

2012

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Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems

2007 IEEE Electrical Performance of Electronic Packaging, 2007, p.29-32

Beyene, W.

2007

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Applications of Multilinear and Waveform Relaxation Methods for Efficient Simulation of Interconnect-Dominated Nonlinear Networks

IEEE transactions on advanced packaging, 2008-08, Vol.31 (3), p.637-648

Beyene, W.T.

2008

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An FDTD-Touchstone hybrid technique for equivalent circuit modeling of SOP electronic packages

IEEE transactions on microwave theory and techniques, 1997-10, Vol.45 (10), p.1911-1918

1997

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Design, modeling, and characterization of passive channels for data rates of 50 Gbps and beyond

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014, p.730-735

2014

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PDN Impedance Optimization of AR/VR Systems: A Trade-off in VRM Bandwidth and Board Decoupling

2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 2024, p.908-912

2024

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Improving a network time-domain measurements with analyzer using a robust rational interpolation technique

IEEE transactions on microwave theory and techniques, 2001-03, Vol.49 (3), p.500-508

Beyene, Wendemagegnehu T

2001

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Optimizing On-Chip Decoupling Capacitors to Improve Power Supply Noise Induced Jitter and ESD Robustness

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.1211-1218

2021

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Improving time-domain measurements with a network analyzer using a robust rational interpolation technique

IEEE transactions on microwave theory and techniques, 2001-03, Vol.49 (3), p.500-508

Beyene, W.T.

2001

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Electrical-thermal co-design of high speed links

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 2010, p.1893-1899

2010

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Accurate frequency-domain modeling and efficient circuit simulation of high-speed packaging interconnects

IEEE transactions on microwave theory and techniques, 1997-10, Vol.45 (10), p.1941-1947

1997

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Peak distortion analysis of nonlinear links

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, 2013, p.169-172

Beyene, Wendemagegnehu T.

2013

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Analysis of Power Supply Noise Induced Jitter of I/O Subsystems with Multiple Power Domains

2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2020, p.1-3

2020

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Black-box modeling of passive systems by rational function approximation

IEEE transactions on advanced packaging, 2005-05, Vol.28 (2), p.209-215

2005

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Toward 224-Gb/s Electrical Signaling-Modulation, Equalization, and Channel Options

Noise and Jitter Characterization of High-Speed Interfaces in Heterogeneous Integrated Systems

Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

Optimal Terminations for Crosstalk Mitigation of High-Speed Interconnects With Discontinuities Using Modal Signaling

Performance analysis and model-to-hardware correlation of multigigahertz parallel bus with transmit pre-emphasis equalization

Properties of mixed-mode parameters of cascaded balanced networks and their applications in modeling of differential interconnects

Low-Order Rational Approximation of Interconnects Using Neural-Network Based Pole-Clustering Techniques

Return loss characterization and analysis of high-speed serial interface

The design of higher-order reference voltage generation circuits for single-ended memory interfaces

Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems

Applications of Multilinear and Waveform Relaxation Methods for Efficient Simulation of Interconnect-Dominated Nonlinear Networks

An FDTD-Touchstone hybrid technique for equivalent circuit modeling of SOP electronic packages

Design, modeling, and characterization of passive channels for data rates of 50 Gbps and beyond

PDN Impedance Optimization of AR/VR Systems: A Trade-off in VRM Bandwidth and Board Decoupling

Improving a network time-domain measurements with analyzer using a robust rational interpolation technique

Optimizing On-Chip Decoupling Capacitors to Improve Power Supply Noise Induced Jitter and ESD Robustness

Improving time-domain measurements with a network analyzer using a robust rational interpolation technique

Electrical-thermal co-design of high speed links

Accurate frequency-domain modeling and efficient circuit simulation of high-speed packaging interconnects

Peak distortion analysis of nonlinear links

Analysis of Power Supply Noise Induced Jitter of I/O Subsystems with Multiple Power Domains

Black-box modeling of passive systems by rational function approximation

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