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Bridging the Gap between RTL and Software Fault Injection

ACM journal on emerging technologies in computing systems, 2021-07, Vol.17 (3), p.1-24

2021

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Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

IET computers & digital techniques, 2009-09, Vol.3 (5), p.487-487

2009

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Design of CMOS MEMS based on mechanical resonators using a RF simulation approach

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-06, Vol.23 (6), p.962-967

2004

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Monolithic piezoresistive CMOS magnetic field sensors

Sensors and actuators. A, Physical, 2003-01, Vol.103 (1), p.23-32

2003

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On the use of an oscillation-based test methodology for CMOS micro-electro-mechanical systems

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002, 2002, p.1120

2002

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Test and Testability of a Monolithic MEMS for Magnetic Field Sensing

Journal of electronic testing, 2001-10, Vol.17 (5), p.439-450

2001

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Mutation Sampling Technique for the Generation of Structural Test Data

Design, Automation and Test in Europe, 2005, p.1022-1023

2005

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Read-Error-Rate evaluation for RFID system on-line testing

2010 IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2010, p.1-6

2010

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Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application: Networks on Chip

IET computers & digital techniques, 2009, Vol.3 (5), p.487-500

2009

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Decreasing Test Qualification Time in AMS and RF Systems

IEEE design & test of computers, 2008-01, Vol.25 (1), p.29-37

2008

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Reliability analysis of CMOS MEMS structures obtained by Front Side Bulk Micromachining

Microelectronics and reliability, 2002, Vol.42 (9), p.1777-1782

2002

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An A/D interface for resonant piezoresistive MEMS sensor

2004 IEEE International Symposium on Industrial Electronics, 2004, Vol.1, p.83-88 vol. 1

2004

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Evaluation of the oscillation-based test methodology for micro-electro-mechanical systems

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2002, p.439-444

2002

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On fault injections for early security evaluation vs. laser-based attacks

2016 1st IEEE International Verification and Security Workshop (IVSW), 2016, p.1-6

2016

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EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement

2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2013, p.20-24

2013

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On error models for RTL security evaluations

2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2014, p.1-6

2014

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Functional Verification of RTL Designs driven by Mutation Testing metrics

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007, p.222-227

2007

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Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology

International Symposium on Quality Electronic Design (ISQED), 2013, p.531-537

2013

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SystemC modeling of RFID systems for robustness analysis

SoftCOM 2011, 19th International Conference on Software, Telecommunications and Computer Networks, 2011, p.1-5

2011

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Laser-induced fault effects in security-dedicated circuits

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC), 2014, p.1-6

2014

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Towards an unified IP verification and robustness analysis platform

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011, p.53-58

2011

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Read rate profile monitoring for defect detection in RFID Systems

2011 IEEE International Conference on RFID-Technologies and Applications, 2011, p.89-94

2011

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A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008, p.149-158

2008

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A DFT Architecture for Asynchronous Networks-on-Chip

Eleventh IEEE European Test Symposium (ETS'06), 2006, p.219-224

2006

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How to Improve a set of design validation data by using mutation-based test

2006 IEEE Design and Diagnostics of Electronic Circuits and systems, 2006, p.75-76

2006

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Bridging the Gap between RTL and Software Fault Injection

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

Design of CMOS MEMS based on mechanical resonators using a RF simulation approach

Monolithic piezoresistive CMOS magnetic field sensors

On the use of an oscillation-based test methodology for CMOS micro-electro-mechanical systems

Test and Testability of a Monolithic MEMS for Magnetic Field Sensing

Mutation Sampling Technique for the Generation of Structural Test Data

Read-Error-Rate evaluation for RFID system on-line testing

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application: Networks on Chip

Decreasing Test Qualification Time in AMS and RF Systems

Reliability analysis of CMOS MEMS structures obtained by Front Side Bulk Micromachining

An A/D interface for resonant piezoresistive MEMS sensor

Evaluation of the oscillation-based test methodology for micro-electro-mechanical systems

On fault injections for early security evaluation vs. laser-based attacks

EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement

On error models for RTL security evaluations

Functional Verification of RTL Designs driven by Mutation Testing metrics

Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology

SystemC modeling of RFID systems for robustness analysis

Laser-induced fault effects in security-dedicated circuits

Towards an unified IP verification and robustness analysis platform

Read rate profile monitoring for defect detection in RFID Systems

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application

A DFT Architecture for Asynchronous Networks-on-Chip

How to Improve a set of design validation data by using mutation-based test

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