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Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

Microprocessors and microsystems, 2021-02, Vol.80, p.103514, Article 103514

2021

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Speed optimal FPGA implementation of the encryption algorithms for telecom applications

Microprocessors and microsystems, 2020-11, Vol.79, p.103324, Article 103324

2020

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Retraction Note to: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications

Journal of ambient intelligence and humanized computing, 2023-04, Vol.14 (Suppl 1), p.555-555

2023

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Lightweight convolutional neural network architecture implementation using TensorFlow lite

International journal of information technology (Singapore. Online), 2023-06, Vol.15 (5), p.2489-2498

2023

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Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis

Wireless personal communications, 2022-12, Vol.127 (3), p.1869-1878

2022

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Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications

Circuits, systems, and signal processing, 2021-06, Vol.40 (6), p.2883-2894

2021

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High‐speed and area‐efficient Sobel edge detector on field‐programmable gate array for artificial intelligence and machine learning applications

Computational intelligence, 2021-08, Vol.37 (3), p.1056-1067

2021

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High-Level synthesis assisted design and verification framework for automotive radar processors

Microprocessors and microsystems, 2020-10, Vol.78, p.103259, Article 103259

2020

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RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications

Journal of ambient intelligence and humanized computing, 2021-07, Vol.12 (7), p.7273-7279

2021

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Dedicated hardware architecture for localizing iris in VW images

Journal of King Saud University. Computer and information sciences, 2022-07, Vol.34 (7), p.4568-4578

2022

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Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images

Engineering science and technology, an international journal, 2017-04, Vol.20 (2), p.694-704

2017

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A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images

Journal of Electrical and Computer Engineering, 2016-01, Vol.2016 (2016), p.413-422

2016

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Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region

International Journal of Reconfigurable Computing, 2015-01, Vol.2015 (2015), p.95-104

2015

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Design and Analysis of a Scan Chain in Subthreshold Region

2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON), 2023, p.1-6

2023

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A Novel Redundant Binary Number to Natural Binary Number Converter

Journal of signal processing systems, 2010-06, Vol.59 (3), p.297-307

2010

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Convolutional Neural Network Hardware Optimization Using Bayesian Method

2024 Second International Conference on Emerging Trends in Information Technology and Engineering (ICETITE), 2024, p.1-7

2024

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Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation

2023 4th IEEE Global Conference for Advancement in Technology (GCAT), 2023, p.1-6

2023

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Low-latency median filter core for hardware implementation of 5 × 5 median filtering

IET image processing, 2017-10, Vol.11 (10), p.927-934

2017

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Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

IET image processing, 2018-10, Vol.12 (10), p.1753-1761

2018

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Hardware Accelerators for Iris Localization

Journal of signal processing systems, 2018-04, Vol.90 (4), p.655-671

2018

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Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm

International journal of electronics, 2018-08, Vol.105 (8), p.1399-1415

2018

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Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes

2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2020, p.1-6

2020

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Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images

International journal of electrical and computer engineering (Malacca, Malacca), 2016-08, Vol.6 (4), p.1637

2016

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Dual channel addition based FFT processor architecture for signal and image processing

International journal of high performance systems architecture, 2009, Vol.2 (1), p.35

2009

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Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems

Microprocessors and microsystems, 2017-06, Vol.51, p.343-355

2017

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Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

Speed optimal FPGA implementation of the encryption algorithms for telecom applications

Retraction Note to: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications

Lightweight convolutional neural network architecture implementation using TensorFlow lite

Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis

Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications

High‐speed and area‐efficient Sobel edge detector on field‐programmable gate array for artificial intelligence and machine learning applications

High-Level synthesis assisted design and verification framework for automotive radar processors

RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications

Dedicated hardware architecture for localizing iris in VW images

Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images

A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images

Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region

Design and Analysis of a Scan Chain in Subthreshold Region

A Novel Redundant Binary Number to Natural Binary Number Converter

Convolutional Neural Network Hardware Optimization Using Bayesian Method

Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation

Low-latency median filter core for hardware implementation of 5 × 5 median filtering

Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

Hardware Accelerators for Iris Localization

Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm

Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes

Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images

Dual channel addition based FFT processor architecture for signal and image processing

Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems

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