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The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study

IEEE transactions on neural networks, 2007-01, Vol.18 (1), p.240-252

2007

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A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)

VLSI Design, 2014-01, Vol.2014 (2014), p.185-195

2014

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Multisource Domain Adaptation for Remote Sensing Using Deep Neural Networks

IEEE transactions on geoscience and remote sensing, 2020-05, Vol.58 (5), p.3328-3340

2020

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Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.480-485

2002

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Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling

VLSI Design, 2013-01, Vol.2013 (2013), p.152-173

2013

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Domain Adaptation Using Representation Learning for the Classification of Remote Sensing Images

IEEE journal of selected topics in applied earth observations and remote sensing, 2017-09, Vol.10 (9), p.4198-4209

2017

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Strength Pareto Particle Swarm Optimization and Hybrid EA-PSO for Multi-Objective Optimization

Evolutionary computation, 2010, Vol.18 (1), p.127-156

2010

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GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures

ACM transactions on design automation of electronic systems, 2018-10, Vol.23 (5), p.1-33

2018

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Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms

ACM transactions on reconfigurable technology and systems, 2010-09, Vol.3 (3), p.1-28

2010

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Modeling leakage power reduction in VLSI as optimization problems

Optimization and engineering, 2007-06, Vol.8 (2), p.129-162

2007

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Machine Learning for Congestion Management and Routability Prediction within FPGA Placement

ACM transactions on design automation of electronic systems, 2020-10, Vol.25 (5), p.1-25

2020

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Design space exploration of Convolutional Neural Networks based on Evolutionary Algorithms

Journal of Computational Vision and Imaging Systems, 2017-10, Vol.3 (1)

2017

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A Deep Learning Framework to Predict Routability for FPGA Circuit Placement

ACM transactions on reconfigurable technology and systems, 2021-09, Vol.14 (3), p.1-28

2021

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A Multilevel Congestion-Based Global Router

VLSI Design, 2009-01, Vol.2009 (2009), p.47-59

2009

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A Deep-Learning Framework for Predicting Congestion During FPGA Placement

2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020, p.138-144

2020

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Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

International Journal of Reconfigurable Computing, 2013-01, Vol.2013 (2013), p.133-165

2013

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A scalable pipelined architecture for real-time computation of MLP-BP neural networks

Microprocessors and microsystems, 2012-03, Vol.36 (2), p.138-150

2012

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Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs

ACM transactions on reconfigurable technology and systems, 2019-09, Vol.12 (3), p.1-25

2019

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Design and optimization of multithreshold CMOS (MTCMOS) circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-10, Vol.22 (10), p.1324-1342

2003

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A Flat Timing-Driven Placement Flow for Modern FPGAs

2019 56th ACM/IEEE Design Automation Conference (DAC), 2019, p.1-6

2019

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Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering

Evolutionary computation, 2004-09, Vol.12 (3), p.327-353

2004

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Corrigendum to “Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm”

International Journal of Reconfigurable Computing, 2018-01, Vol.2018 (2018), p.1-1

2018

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GPlace: A congestion-aware placement tool for UltraScale FPGAs

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, p.1-7

2016

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An adaptive encryption based genetic algorithms for medical images

2013 IEEE International Workshop on Machine Learning for Signal Processing (MLSP), 2013, p.1-6

2013

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Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), 2002, p.480-485

2002

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The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study

A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)

Multisource Domain Adaptation for Remote Sensing Using Deep Neural Networks

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling

Domain Adaptation Using Representation Learning for the Classification of Remote Sensing Images

Strength Pareto Particle Swarm Optimization and Hybrid EA-PSO for Multi-Objective Optimization

GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures

Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms

Modeling leakage power reduction in VLSI as optimization problems

Machine Learning for Congestion Management and Routability Prediction within FPGA Placement

Design space exploration of Convolutional Neural Networks based on Evolutionary Algorithms

A Deep Learning Framework to Predict Routability for FPGA Circuit Placement

A Multilevel Congestion-Based Global Router

A Deep-Learning Framework for Predicting Congestion During FPGA Placement

Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

A scalable pipelined architecture for real-time computation of MLP-BP neural networks

Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs

Design and optimization of multithreshold CMOS (MTCMOS) circuits

A Flat Timing-Driven Placement Flow for Modern FPGAs

Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering

Corrigendum to “Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm”

GPlace: A congestion-aware placement tool for UltraScale FPGAs

An adaptive encryption based genetic algorithms for medical images

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

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