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Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2012-12, Vol.59 (12), p.3510-3518

2012

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Analysis of the leakage current in junctionless nanowire transistors

Applied physics letters, 2013-11, Vol.103 (20)

2013

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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Solid-state electronics, 2022-08, Vol.194, p.108337, Article 108337

2022

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Junctionless Multiple-Gate Transistors for Analog Applications

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2511-2519

2011

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Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors

Journal of computational electronics, 2022-06, Vol.21 (3), p.654-665

2022

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Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

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Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

IEEE journal of the Electron Devices Society, 2021, Vol.9, p.492-499

2021

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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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The zero temperature coefficient in junctionless nanowire transistors

Applied physics letters, 2012-08, Vol.101 (6), p.62101

2012

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Electrical characterization of vertically stacked p-FET SOI nanowires

Solid-state electronics, 2018-03, Vol.141, p.84-91

2018

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Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates

Solid-state electronics, 2013-12, Vol.90, p.121-126

2013

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Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

Solid-state electronics, 2012-04, Vol.70, p.39-43

2012

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.12 (2), p.56-61

Pavanello, Marcelo Antonio

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.12 (1), p.1-6

Pavanello, Marcelo Antonio

2020

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Temperature Measurement of a Nanowire SOI Transistor Using a Parallel Gated SOI PIN Diode

Journal of Integrated Circuits and Systems, 2024-08, Vol.19 (2), p.1-9

2024

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.7 (2), p.81-86

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.7 (1), p.1-6

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.6 (2), p.81-86

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.6 (1), p.1-6

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.9 (1), p.1-6

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.11 (2), p.69-74

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.11 (3), p.140-146

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.11 (1), p.1-6

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.10 (1), p.1-6

2020

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Table of Contents and Foreword

Journal of Integrated Circuits and Systems, 2020-12, Vol.9 (2), p.80-86

2020

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Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

Analysis of the leakage current in junctionless nanowire transistors

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Junctionless Multiple-Gate Transistors for Analog Applications

Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors

Analog characteristics of n-type vertically stacked nanowires

Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

The zero temperature coefficient in junctionless nanowire transistors

Electrical characterization of vertically stacked p-FET SOI nanowires

Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates

Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

Table of Contents and Foreword

Table of Contents and Foreword

Temperature Measurement of a Nanowire SOI Transistor Using a Parallel Gated SOI PIN Diode

Table of Contents and Foreword

Table of Contents and Foreword

Table of Contents and Foreword

Table of Contents and Foreword

Table of Contents and Foreword

Table of Contents and Foreword

Table of Contents and Foreword

Table of Contents and Foreword

Table of Contents and Foreword

Table of Contents and Foreword

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