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Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates

IEEE transactions on circuits and systems. I, Regular papers, 2021-03, Vol.68 (3), p.1217-1230

2021

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MR-PIPA: An Integrated Multilevel RRAM (HfOx)-Based Processing-In-Pixel Accelerator

IEEE journal on exploratory solid-state computational devices and circuits, 2022-12, Vol.8 (2), p.59-67

2022

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Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks

Journal of low power electronics and applications, 2022-12, Vol.12 (4), p.57

2022

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PANDA: Processing in Magnetic Random-Access Memory-Accelerated de Bruijn Graph-Based DNA Assembly

Journal of low power electronics and applications, 2024-03, Vol.14 (1), p.9

2024

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Enabling Intelligent IoTs for Histopathology Image Analysis Using Convolutional Neural Networks

Micromachines (Basel), 2022-08, Vol.13 (8), p.1364

2022

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A combined three and five inputs majority gate-based high performance coplanar full adder in quantum-dot cellular automata

International journal of information technology (Singapore. Online), 2021-06, Vol.13 (3), p.1165-1177

2021

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MRIMA: An MRAM-Based In-Memory Accelerator

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-05, Vol.39 (5), p.1123-1136

2020

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ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019, p.1-8

2019

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An efficient majority-based compressor for approximate computing in the nano era

Microsystem technologies : sensors, actuators, systems integration, 2018-03, Vol.24 (3), p.1589-1601

2018

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Design of an ultra-efficient reversible full adder-subtractor in quantum-dot cellular automata

Optik (Stuttgart), 2017-08, Vol.142, p.557-563

2017

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IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018, p.111-116

2018

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AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM

2019 56th ACM/IEEE Design Automation Conference (DAC), 2019, p.1-6

2019

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PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation

Proceedings of the 55th Annual Design Automation Conference, 2018, p.1-6

2018

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Hybrid Spin-CMOS Polymorphic Logic Gate With Application in In-Memory Computing

IEEE transactions on magnetics, 2020-02, Vol.56 (2), p.1-15

2020

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Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata

Journal of low-power electronics, 2014-06, Vol.10 (2), p.259-271

2014

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Enabling Normally-Off In Situ Computing With a Magneto-Electric FET-Based SRAM Design

IEEE transactions on electron devices, 2024-04, Vol.71 (4), p.2742-2748

2024

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AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration

IEEE journal on emerging and selected topics in circuits and systems, 2023-03, Vol.13 (1), p.225-236

2023

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Semi-decentralized Inference in Heterogeneous Graph Neural Networks for Traffic Demand Forecasting: An Edge-Computing Approach

IEEE transactions on vehicular technology, 2024, p.1-16

2024

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Design and Evaluation of a Near-Sensor Magneto-Electric FET-Based Event Detector

IEEE transactions on electron devices, 2023-09, Vol.70 (9), p.4822-4828

2023

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DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-6

2024

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LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking

IEEE computer architecture letters, 2022-07, Vol.21 (2), p.141-144

2022

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GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.378-383

2019

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Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-09, Vol.37 (9), p.1788-1801

2018

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Efficient and Robust SRAM Cell Design Based on Quantum-Dot Cellular Automata

ECS journal of solid state science and technology, 2018, Vol.7 (3), p.Q38-Q45

2018

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Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM

2017 IEEE International Conference on Computer Design (ICCD), 2017, p.609-612

2017

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Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates

MR-PIPA: An Integrated Multilevel RRAM (HfOx)-Based Processing-In-Pixel Accelerator

Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks

PANDA: Processing in Magnetic Random-Access Memory-Accelerated de Bruijn Graph-Based DNA Assembly

Enabling Intelligent IoTs for Histopathology Image Analysis Using Convolutional Neural Networks

A combined three and five inputs majority gate-based high performance coplanar full adder in quantum-dot cellular automata

MRIMA: An MRAM-Based In-Memory Accelerator

ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations

An efficient majority-based compressor for approximate computing in the nano era

Design of an ultra-efficient reversible full adder-subtractor in quantum-dot cellular automata

IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network

AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM

PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation

Hybrid Spin-CMOS Polymorphic Logic Gate With Application in In-Memory Computing

Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata

Enabling Normally-Off In Situ Computing With a Magneto-Electric FET-Based SRAM Design

AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration

Semi-decentralized Inference in Heterogeneous Graph Neural Networks for Traffic Demand Forecasting: An Edge-Computing Approach

Design and Evaluation of a Near-Sensor Magneto-Electric FET-Based Event Detector

DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems

LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking

GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption

Efficient and Robust SRAM Cell Design Based on Quantum-Dot Cellular Automata

Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM

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