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3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

IEEE journal of solid-state circuits, 2006-08, Vol.41 (8), p.1718-1725

2006

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An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.884-896

2012

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Atomic-beam alignment of inorganic materials for liquid-crystal displays

Nature (London), 2001-05, Vol.411 (6833), p.56-59

2001

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Three-dimensional silicon integration

IBM journal of research and development, 2008-11, Vol.52 (6), p.553-569

2008

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Electroless Deposition of NiB on 15 Inch Glass Substrates for the Fabrication of Transistor Gates for Liquid Crystal Displays

Langmuir, 2003-07, Vol.19 (14), p.5923-5935

2003

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3-D Die Stacking With 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System

IEEE transactions on components, packaging, and manufacturing technology (2011), 2021-05, Vol.11 (5), p.875-878

2021

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Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

IBM journal of research and development, 2008-11, Vol.52 (6), p.571-581

2008

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3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

IBM journal of research and development, 2008-11, Vol.52 (6), p.611-622

2008

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Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

IBM journal of research and development, 2005-07, Vol.49 (4.5), p.725-753

2005

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3D chip stacking with C4 technology

IBM journal of research and development, 2008-11, Vol.52 (6), p.599-609

2008

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Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

IEEE electron device letters, 2010-12, Vol.31 (12), p.1461-1463

2010

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An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.C192-C193

2015

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CMOS-Compatible Through Silicon Vias for 3D Process Integration

MRS proceedings, 2006, Vol.970, Article 0970-Y01-01

2006

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Simulation of thermal pulse evolution during laser debonding

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015, p.1423-1429

2015

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Direct Bonded Heterogeneous Integration (DBHi) Si Bridge

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.136-147

2021

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Driving large-sized OLED TVs with an amorphous-silicon backplane

Journal of the Society for Information Display, 2005-02, Vol.13 (2), p.161-167

2005

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U of T Weighs In on Formocresol Debate [Response to article: Do we still need formocresol in pediatric dentistry? 2005; 71(10):749-51]

Journal (Canadian Dental Association), 2005-12, Vol.71 (11), p.801

2005

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3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55\ \mu\mathrm-75\ \mu \mathrm Mixed Pitch Interconnections on High Density Laminate

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.292-297

2021

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Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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Injection of Molten Solder (IMS) Technology for Solder Bumping on Wafers, Ceramic/Organic/Flexible Substrates, and Si Via Filling from Fine Pitch to Large Pitch

2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.663-668

2018

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Silicon‐Based Packaging and Silicon Micromachining

Advanced Millimeter‐Wave Technologies, 2009, p.771-812

2009

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Floating-island TFT leakage caused by process step reduction

IEEE transactions on electron devices, 2002-04, Vol.49 (4), p.576-583

2002

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Factors in the selection of temporary wafer handlers for 3D/2.5D integration

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014, p.576-581

2014

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Column Interconnects: A Path Forward for Embedded Cooling of High Power 3D Chip Stacks

2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.97-102

2018

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Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.659-662

2005

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3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

Atomic-beam alignment of inorganic materials for liquid-crystal displays

Three-dimensional silicon integration

Electroless Deposition of NiB on 15 Inch Glass Substrates for the Fabrication of Transistor Gates for Liquid Crystal Displays

3-D Die Stacking With 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

3D chip stacking with C4 technology

Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors

CMOS-Compatible Through Silicon Vias for 3D Process Integration

Simulation of thermal pulse evolution during laser debonding

Direct Bonded Heterogeneous Integration (DBHi) Si Bridge

Driving large-sized OLED TVs with an amorphous-silicon backplane

U of T Weighs In on Formocresol Debate [Response to article: Do we still need formocresol in pediatric dentistry? 2005; 71(10):749-51]

3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55\ \mu\mathrm-75\ \mu \mathrm Mixed Pitch Interconnections on High Density Laminate

Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits

Injection of Molten Solder (IMS) Technology for Solder Bumping on Wafers, Ceramic/Organic/Flexible Substrates, and Si Via Filling from Fine Pitch to Large Pitch

Silicon‐Based Packaging and Silicon Micromachining

Floating-island TFT leakage caused by process step reduction

Factors in the selection of temporary wafer handlers for 3D/2.5D integration

Column Interconnects: A Path Forward for Embedded Cooling of High Power 3D Chip Stacks

Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology

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